US 6,307,217 B1Granted

Semiconductor memory device having driver and load MISFETs and capacitor elements

AssigneesHitachi, Ltd., Hitachi ULSI Engineering Corp.

InventorsShuji Ikeda, Satoshi Meguro, Kyoichiro Asayama, Eri Fujita, Koichiro Ishibashi, Toshiro Aoto, Sadayuki Morita, Atsuyoshi Koike, Masayuki Kojima, Yasuo Kiguchi, Kazuyuki Suko, Fumiyuki Kanai, Naotaka Hashimoto, Toshiaki Yamanaka

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Abstract

A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.

Claims36

Dependent claims

A semiconductor integrated circuit device, comprising:

a semiconductor substrate having a main surface;
a plurality of memory cells of a static random access memory, said plurality of memory cells being arranged in a row and a column direction, each of said plurality of memory cells including a first driver MISFET and a second driver MISFET and a first load MISFET and a second load MISFET;
each of said first and said second driver MISFETs having a gate electrode overlying said main surface and a source region and a drain region in said semiconductor substrate;
a first insulating film overlying said first and said second driver MISFETs so as to cover said main surface;
first conductive strips overlying said first insulating film, wherein a source region, a drain region and a channel-forming region of each of said first and second load MISFETs are provided in said first conductive strips, and wherein the drain regions of said first and second load MISFETs are electrically connected to the drain regions of said first and second driver MISFETs, respectively;
gate electrodes of said first and second load MISFETs, overlying said first conductive strips, wherein said gate electrodes of said first and second load MISFETs are electrically connected to said drain regions of said second and first driver MISFETs, respectively;
gate insulating films of said first and second load MISFETs, provided between the channel-forming regions and the gate electrodes thereof;
a second insulating film overlying said first conductive strips and said gate electrodes of said first and said second load MISFETs;
and
a power source applying layer overlying said second insulating film so as to cover said plurality of memory cells, said power source applying layer being electrically connected to the source regions of said first and second load MISFETs of said plurality of memory cells, said gate electrodes of said first and said second load MISFETs, said second insulating film and said power source applying layer constituting capacitor elements.

7 more elements

A semiconductor integrated circuit device, comprising:

a semiconductor substrate having a main surface;
a plurality of memory cells of a static random access memory, each of said plurality of memory cells including (1) transfer MISFETs controlled by word lines, and (2) a flip-flop circuit including driver MISFETs and load MISFETs;
first conductive strips overlying said main surface of said semiconductor substrate and providing gate electrodes of said driver MISFETs;
second conductive strips overlying said main surface of said semiconductor substrate and providing gate electrodes of said transfer MISFETs;
third conductive strips overlying said first and said second conductive strips and each including a channel-forming region, a source region and a drain region of a load MISFET;
fourth conductive strips overlying said third conductive strips and providing gate electrodes of said load MISFETs;
a supply voltage layer overlying said fourth conductive strips and being connected to said source regions of said load MISFETs;
and
a dielectric film provided between said gate electrodes of said load MISFETs and said supply voltage layer;
wherein said supply voltage layer, dielectric film and load MISFETs are positioned relative to one another so that capacitor elements are formed between said gate electrodes of said load MISFETs and said supply voltage layer, with said dielectric film serving as a dielectric of said capacitor elements.

7 more elements

A semiconductor integrated circuit device, comprising:

a semiconductor substrate having a main surface;
a plurality of memory cells, each of said plurality of memory cells including a first driver MISFET and a second driver MISFET, each of the first and second driver MISFETs having source and drain regions, a first load element and a second load element, and first and second transfer MISFETs controlled by word lines, each of the first and second transfer MISFETs having source and drain regions, wherein each of the source and drain regions of the driver MISFETs has double-diffused drain structure, and each of the source and drain regions of the transfer MISFETs has lightly doped drain structure, wherein the lightly doped drain structure of each of the transfer MISFETs includes a low impurity concentration region of a first conductivity type adjacent a channel-forming region of the transfer MISFETs and a high impurity concentration region of said first conductivity type adjacent said low impurity concentration region, and wherein a low impurity concentration region of a second conductivity type, opposite the first conductivity type, is provided underlying the low impurity concentration region of the first conductivity type, the device further comprising peripheral circuits, wherein the peripheral circuits further include asymmetrical structured n-channel MISFETs each having a source region of a double-diffused drain structure comprised of a relatively high-concentration n-type semiconductor region and a relatively low-concentration n-type semiconductor region surrounding said relatively high-concentration n-type semiconductor region, said asymmetrical structured n-channel MISFETs each having a drain region with the same lightly doped drain structure as that of the transfer MISFETs.

A semiconductor memory device, comprising:

a semiconductor substrate having a main surface;
a plurality of memory cells of a static random access memory arranged in a row and a column direction, each of said plurality of memory cells including a first driver MISFET and a second driver MISFET, and a first load MISFET and a second load MISFET;
each of said first and second driver MISFETs having a source region and a drain region in said semiconductor substrate, and a gate electrode over said main surface;
a source region, a drain region, and a channel-forming region of said first load MISFET being provided in a first conductive strip;
a source region, a drain region, and a channel-forming region of said second load MISFET being provided in a second conductive strip;
each of said first conductive strip and said second conductive strip being formed over a respective one of said gate electrodes of said first and second driver MISFETs;
a gate electrode of said first load MISFET provided over said channel-forming region of said first load MISFET and electrically connected to both said gate electrode of said first driver MISFET and said drain region of said second driver MISFET;
a gate electrode of said second load MISFET provided over said channel-forming region of said second load MISFET and electrically connected to both said gate electrode of said second driver MISFET and said drain region of said first driver MISFET;
a silicon nitride film provided over said gate electrodes of said first and second load MISFETs and said source and drain regions of said first and second load MISFETs so as to cover said gate electrodes of said first and second load MISFETs and said source and drain regions of said first and second load MISFETs;
and
a first voltage supplying layer provided over said silicon nitride film so as to cover said silicon nitride film,
said gate electrodes of said first and second load MISFETs, said first voltage supplying layer, and said silicon nitride film constituting capacitor elements.

9 more elements

A semiconductor memory device, comprising:

a semiconductor substrate having a main surface;
a plurality of memory cells of a static random access memory arranged in a row direction and a column direction, each of said plurality of memory cells including a first driver MISFET and a second driver MISFET, and a first load MISFET and a second load MISFET;
each of said first and second driver MISFETs having a source region and a drain region in said semiconductor substrate, and a gate electrode over said main surface;
a source region, a drain region, and a channel-forming region of said first load MISFET being provided in a first conductive strip;
a source region, a drain region, and a channel-forming region of said second load MISFET being provided in a second conductive strip;
each of said first and said second conductive strips being provided over a respective one of said gate electrodes of said driver MISFETs;
a gate electrode of said first load MISFET provided over said channel-forming region of said first load MISFET and electrically connected to both said gate electrode of said first driver MISFET and said drain region of said second driver MISFET;
a gate electrode of said second load MISFET provided over said channel-forming region of said second load MISFET and electrically connected to both said gate electrode of said second driver MISFET and said drain region of said first driver MISFET;
a first voltage supplying layer provided over said gate electrodes of said first and second load MISFETs and electrically connected to said source regions of said first and second load MISFETs, wherein said first voltage supplying layer is continuously provided extending diagonally relative to said row and said column directions to extend over said plurality of memory cells arranged in said row and said column directions;
and
a second voltage supplying layer provided over said gate electrodes of said driver MISFETs, below said first and second conductive strips, and electrically connected to said source regions of said first and second driver MISFETs, wherein said second voltage supplying layer is continuously provided extending diagonally relative to said row and said column directions to extend over said plurality of memory cells arranged in said row and said column directions;
a first insulating film over said first voltage supplying layer;
and
pairs of data lines over said first insulating film, each of said pairs comprised of complementary data lines extending in said row direction;
each of said plurality of memory cells further including a first transfer MISFET and a second transfer MISFET, each having a source region and a drain region;
said first voltage supplying layer having openings such that in viewing a plane in parallel with said main surface, within said memory cell, one opening is spaced apart from another opening diagonally relative to said row direction and said column direction, and such that in viewing a plane in parallel with said main surface, within said memory cell, said first load MISFET and said second load MISFET are arranged between said one opening and said another opening;
said first insulating film having first and second contact holes such that in viewing a plane parallel with said main surface, within said memory cell, said first and second contact holes are positioned over portions of said first voltage supplying layer where said one and said another openings are formed, respectively, such that one of said source and drain regions of said first transfer MISFET is electrically connected to one of said complementary data lines through said first contact hole, and such that one of said source and drain regions of said second transfer MISFET is electrically connected to another of said complementary data lines through said second contact hole.

14 more elements

A semiconductor memory device, comprising:

a semiconductor substrate having a main surface;
a plurality of memory cells of a static random access memory arranged in a row direction and a column direction, each of said plurality of memory cells including first and second transfer MISFETs, first and second driver MISFETs, and first and second load MISFETs;
each of said first and second driver MISFETs having a source region and a drain region in said semiconductor substrate, and a gate electrode over said main surface;
each of said first and second transfer MISFETs having a source region and a drain region in said semiconductor substrate, and a gate electrode over said main surface;
a source region, a drain region, and a channel-forming region of said first load MISFET being provided in a first conductive strip;
a source region, a drain region, and a channel-forming region of said second load MISFET being provided in a second conductive strip;
each of said first and said second conductive strips being formed over a respective one of said gate electrodes of said first and second driver MISFETs;
a gate electrode of said first load MISFET provided over said channel-forming region of said first load MISFET and electrically connected to both said gate electrode of said first driver MISFET and said drain region of said second driver MISFET;
a gate electrode of said second load MISFET provided over said channel-forming region of said second load MISFET and electrically connected to both said gate electrode of said second driver MISFET and said drain region of said first driver MISFET;
a first insulating film provided over said gate electrodes of said first and second load MISFETs and said first conductive strip;
a first voltage supplying layer over said first insulating film and electrically connected to said source regions of said first and second load MISFETs, said first voltage supplying layer continuously provided extending diagonally relative to said row and said column directions to extend over said plurality of memory cells arranged in said row and said column directions;
a second insulating film provided over said first voltage supplying layer;
and
pairs of data lines formed over said second insulating film, each of said pairs comprised of complementary data lines extending in said row direction,
said first voltage supplying layer having openings such that in viewing a plane in parallel with said main surface, within said memory cell, one opening is spaced apart from another opening diagonally relative to said row direction and said column direction, and such that in viewing a plane in parallel with said main surface, within said memory cell, said first and said second load MISFETs are arranged between said one opening and said another opening,
said second insulating film having first and second contact holes such that in viewing a plane in parallel with said main surface, within said memory cell, said first and second contact holes are positioned over portions of said first voltage supplying layer where said one and said another opening are formed, respectively, such that one of said source and drain regions of said first transfer MISFET is electrically connected to one of said complementary data lines through said first contact hole, and such that one of said source and drain regions of said second transfer MISFET is electrically connected to another of said complementary data lines through said second contact hole,
said first insulating film having third and fourth contact holes such that in viewing a plane in parallel with said main surface, said third contact hole is positioned between adjacent first contact holes in said column direction, such that in viewing a plane in parallel with said main surface, said fourth contact hole is positioned between adjacent second contact holes in said column direction, and such that in viewing a plane in parallel with said main surface, within said memory cell, said first voltage supplying layer is electrically connected to said source regions of said first and second load MISFETs through said third and fourth contact holes, respectively.

14 more elements

Dependencies are inferred from the claim text.