Method for forming wiring with extremely low parasitic capacitance

#This invention relates generally to the fabrication of semiconductor devices and more particularly to the use of air gaps as a low-dielectric constant material between metal lines and features.

#The trend in the semiconductor industry toward smaller devices and more densely packed designs on microelectronic substrates continues to create new challenges. One of the more recent obstacles to improvements in device performance is the need to reduce the dielectric constant of the materials between closely packed metal lines in a metallization layer. Metal lines in close proximity within a metallization layer have a parasitic capacitance which can lead to ‘cross-talk’ between lines as well as slower device performance.

#One method for reducing the parasitic capacitance between nearby metal lines is to reduce the effective dielectric constant between the metal lines. Ideally, the dielectric constant between the metal lines could be reduced to 1, the dielectric constant of vacuum and the theoretical minimum. Traditionally the space between metal lines has been filled with SiO2, which typically exhibits dielectric constants between 3.5-4.0. All of the technological problems associated with working with SiO2 are well-characterized, so SiO2 provides a convenient material as the interlayer dielectric. SiO2 also has the necessary structural integrity to support the multiple levels present in modern multi-level metallization stacks used to connect densely packed devices.

#FIG. 1 is a schematic cross-sectional view of a substrate undergoing the process of a preferred embodiment of the invention.

#FIG. 2 is a more detailed schematic cross-sectional view of a substrate in the vicinity of a metal feature.

#FIG. 3 shows the substrate of FIG. 1 at a processing step subsequent to that shown in FIG. 1.

#In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention.

#The terms “wafer” and “substrate” are to be understood as including any semiconductor-based structure which may be beneficially treated by the process of this invention. “Wafer” or “substrate” may include silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” or “substrate” in the following description, previous process steps may have been utilized to form regions or junctions in the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, germanium, or gallium arsenide.

#The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.