Method of patterning gate electrodes with high K gate dielectrics

A method of forming a gate electrode, comprising the following steps:

• providing a silicon substrate having at least one active area;
• a buffer layer overlies said silicon substrate and a gate dielectric layer overlies said buffer layer;
• said buffer layer being from about 3 to 10 Å thick;
• said gate dielectric layer being from about 10 to 50 Å thick;
• forming a sacrificial oxide layer over said gate dielectric layer;
• forming a nitride layer over said sacrificial oxide layer;
• said nitride layer being from about 2250 to 2750 Å thick;
• patterning said nitride layer to form an opening therein within said active area exposing a portion of said sacrificial oxide layer within said opening;
• stripping said portion of said sacrificial oxide layer within said opening exposing a portion of said underlying gate dielectric layer within said opening;
• forming a gate electrode within said opening over said portion of said gate dielectric layer;
• selectively removing said remaining nitride layer;
• and
• stripping and removing said remaining sacrificial oxide layer.

A method of forming a gate electrode, comprising the following steps:

• providing a silicon substrate having at least one active area;
• a buffer layer overlies said silicon substrate and a gate dielectric layer overlies said buffer layer;
• said buffer layer being from about 3 to 10 Å thick;
• said gate dielectric layer being from about 10 to 50 Å thick;
• forming a sacrificial oxide layer over said gate dielectric layer;
• forming a nitride layer over said sacrificial oxide layer;
• said nitride layer being from about 2250 to 2750 Å thick;
• forming and patterning a layer of photoresist over said nitride layer to form a gate reverse mask;
• etching said nitride layer through said gate reverse mask to form an opening therein within said active area exposing a portion of said sacrificial oxide layer within said opening;
• stripping said portion of said sacrificial oxide layer within said opening exposing a portion of said underlying gate dielectric layer within said opening;
• forming a gate electrode within said opening over said portion of said gate dielectric layer;
• selectively removing said remaining nitride layer;
• and
• stripping and removing said remaining sacrificial oxide layer.