US 6,306,715 B1Granted

Method to form smaller channel with CMOS device by isotropic etching of the gate materials

AssigneeChartered Semiconductor Manufacturing Ltd.

InventorsLap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng

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Abstract

A method to form a MOS transistor with a narrow channel regions and a wide top (second) gate portion. A gate dielectic layer and a first gate layer are formed over a substrate. A second gate portion is formed over the first gate layer. Spacers are formed on the sidewalls of the second gate portion. In a critical step, we isotropically etch the first gate layer to undercut the second gate portion to form a first gate portion so that the first portion has a width less than the second gate portion. The spacers are removed. Lightly doped drains, sidewall spacers and source/drain regions are formed to complete the device.

Claims14

Dependent claims

A method of fabrication of CMOS transistor having a smaller channel;

comprising the steps of:
a) forming a gate dielectric layer over a substrate;
b) forming a first gate layer over said gate dielectric layer;
c) forming a second gate layer over said first gate layer;
d) patterning said second gate layer to form a second gate portion over said first gate layer;
e) forming spacers on the sidewalls of said second gate portion;
f) isotropically etching said first gate layer to undercut said second gate portion to form a first gate portion so that said first gate portion has a width less than said second gate portion;
g) removing said spacers;
h) forming lightly doped drains adjacent to said first gate portion and under said second gate portion;
i) forming sidewall spacers on the sidewalls of said first and second gate portions;
and
j) forming source/drain regions adjacent to said sidewall spacers.

9 more elements

A method of fabrication of CMOS transistor having a smaller channel, comprising the steps of:

a) forming a gate dielectric layer over a substrate;
b) gate dielectric layer formed of a material selected from the group consisting of silicon oxide, tantalum oxide, silicon nitride, zirconium oxide, Hafnium oxide and titanium oxide;
c) forming a first gate layer over said gate dielectric layer;
(1) said a first gate layer has a thickness of between about 500 and 1000 Å;
(2) said first gate layer comprised of polysilicon, TiN or Ta;
d) forming a second gate layer over said first gate layer;
said second gate layer and said first gate layer have an etch rate ratio greater than 5:1;
(1) said second gate layer comprised of W, Ta, or tungsten silicide;
(2) said second gate layer having a thickness of between about 500 and 1000 Å;
e) forming a cap layer over said second gate layer;
said cap layer comprised of silicon oxide;
f) patterning said second gate layer and said cap layer to form a cap and a second gate portion over said first gate layer;
g) forming spacers on the sidewalls of said second gate portion;
(1) said spacers are comprised of silicon oxide and have a thickness of between about 200 and 600 Å;
h) isotropically etching said first gate layer to undercut said second gate portion to form a first gate portion so that said first gate portion has a width less than said second gate portion;
(1) the isotropic etch comprising a Cl2/O2 etch chemistry or SF6/Cl2/O2 etch chemistry;
(2) said first gate portion is narrower than said second gate portion by between about 10 to 20%;
i) removing said spacers;
j) forming lightly doped drains adjacent to said first gate portion and under said second gate portion;
(1) said lightly doped drains formed using an angled ion implant so that the lightly doped drain is implanted under the second gate portion and said first gate portion;
k) forming sidewall spacers on the sidewalls of said first and second gate portions;
and
l) forming source/drain regions adjacent to said sidewall spacers.

20 more elements

Dependencies are inferred from the claim text.