US 6,306,714 B1Granted

Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide

AssigneeChartered Semiconductor Manufacturing Ltd.

InventorsYang Pan, James Yongmeng Lee, Ying Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan

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Abstract

A method of fabrication of an elevated source/drain (S/D) for a MOS device. A first insulating layer having a gate opening and source/drain openings is formed over a substrate. We form a LDD resist mask having opening over the source/drain openings over the first insulating layer. Ions are implanted through the source/drain openings. A first dielectric layer is formed on the substrate in the gate opening and source/drain openings. A gate is formed in the gate opening and raised source/drain (S/D) blocks in the source/drain openings. We remove the spacer blocks to form spacer block openings. We form second LDD regions by implanting ions through the spacer block openings. We form second spacer blocks in the spacer block openings. Plug opening are formed through the raised source/drain (S/D) blocks. Contact plugs are formed in the form plug opening.

Claims15

Dependent claims

A method of fabrication of an elevated source/drain (S/D) for a MOS device;

comprising the steps of:
a) forming a first insulating layer over a substrate;
b) forming a gate opening and source/drain openings in said first insulating layer exposing said substrate;
said gate opening defines a channel region in said substrate;
said source/drain (S/D) openings define first LDD source/drain area in said substrate;
said gate opening and said source/drain (S/D) openings defining spacer blocks of said first insulating layer;
c) forming a LDD resist mask having openings over said source/drain openings in said first insulating layer;
d) implanting ions through said source/drain openings form said first lightly doped drain regions in said substrate;
e) removing said LDD resist mask;
f) forming a first dielectric layer on said substrate in said gate opening and source/drain openings;
g) forming a gate in said gate opening and raised source/drain (S/D) blocks in said source/drain openings;
h) removing said spacer blocks to form spacer block openings;
i) forming second LDD regions by implanting ions through said spacer block openings;
j) forming second spacer blocks in said spacer block openings;
k) forming plug opening through said raised source/drain (S/D) blocks;
and
l) forming contact plugs in said plug opening.

14 more elements

A method of fabrication of an elevated source/drain (S/D) for a MOS device;

comprising the steps of:
a) forming a first insulating layer over a substrate;
(1) said first insulating layer has a thickness of between about 1000 and 3000 Å;
b) forming a gate opening and source/drain openings in said first insulating layer exposing said substrate;
said gate opening defines a channel region in said substrate;
said source/drain (S/D) openings define first LDD source/drain area in said substrate;
said gate opening and said source/drain (S/D) openings defining spacer blocks of said first insulating layer;
c) forming a LDD resist mask having openings over said source/drain openings in said first insulating layer;
d) implanting ions through said source/drain openings form said first lightly doped drain regions in said substrate;
e) removing said LDD resist mask;
f) forming a first dielectric layer on said substrate in said gate opening and source/drain openings;
(1) said first dielectric layer is comprised of silicon oxide and has a thickness of between about 20 and 50 Å;
g) forming a gate in said gate opening and raised source/drain (S/D) blocks in said source/drain openings;
(1) said gate and said raised source/drain (S/D) blocks are fabricated by forming a conductive layer over said first insulating layer and said first dielectric layer and chemical-mechanical polish (CMP) said conductive layer;
(2) said gate and said raised source/drain (S/D) blocks are comprised of polysilicon;
h) removing said spacer blocks to form spacer block openings;
i) forming second LDD regions by implanting ions through said spacer block openings;
j) forming second spacer blocks in said spacer block openings;
k) forming plug opening through said raised source/drain (S/D) blocks;
l) forming contact plugs in said plug opening;
(1) said contact plugs are comprised of tungsten (W) formed by depositing a blanket W layer and chemical-mechanical polishing (CMP) said blanket W layer.

18 more elements

A method of fabrication of an elevated source/drain (S/D) for an MOS device;

comprising the steps of:
a) forming a first insulating layer over a substrate;
(1) said first insulating layer is comprised of silicon oxide;
(2) said first insulating layer having a thickness of between about 1000 and 3000 Å;
b) forming gate opening and source/drain openings in said first insulating layer exposing said substrate;
said gate opening defines a channel region in said substrate;
said source/drain (S/D) openings define first LDD source/drain area in said substrate;
said gate opening and said source/drain (S/D) openings defining spacer blocks of said first insulating layer;
c) forming a LDD resist mask having openings over said source/drain openings in said first insulating layer;
d) implanting ions through said source/drain openings form said first lightly doped drain regions in said substrate;
(1) said first lightly doped drain regions have a concentration between 1E17 and 1E18 atom/cc and a depth between about 0.08 and 0.15 μm;
e) removing said LDD resist mask;
f) forming a first dielectric layer on said substrate in said gate opening and source/drain openings;
(1) said first dielectric layer is comprised of silicon oxide and has a thickness of between about 20 and 50 Å;
g) forming a gate in said gate opening and raised source/drain (S/D) blocks in said source/drain openings;
(1) said gate and said raised source/drain (S/D) blocks are fabricated by forming a conductive layer over said first insulating layer and said first dielectric layer and chemical-mechanical polish (CMP) said conductive layer;
(2) said gate and said raised source/drain (S/D) blocks are comprised of polysilicon;
h) removing said spacer blocks to form spacer block openings;
i) forming second LDD regions by implanting ions through said spacer block openings;
(1) said second lightly doped drain regions having a concentration between 1E17 and 1E19 atom/cc and a depth between about 200 and 1500 Å;
j) forming second spacer blocks in said spacer block openings;
k) forming plug opening through said raised source/drain (S/D) blocks;
l) forming contact plugs in said plug opening;
(1) said contact plugs is comprised of tungsten (W) formed by depositing a blanket W layer and chemical-mechanical polishing (CMP) said blanket W layer.

21 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/713,802Filed 16 Nov 2000
Granted: 23 Oct 2001
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10W 20/056
Of conductive parts of the interconnections: by filling conductive material into holes, grooves or trenches
H10D 30/022
Of FETs having insulated gates [IGFET]: having lightly-doped source or drain extensions selectively formed at the sides of the gates
H10D 30/0225
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: using an initial gate mask complementary to the…
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…