Fabrication of a gate structures having a longer length toward the top for formation of a rectangular shaped spacer

A method for fabricating a gate structure of a field effect transistor on a semiconductor substrate, the method including the steps of:

• A. depositing a layer of gate structure material on said semiconductor substrate;
• B. adjusting a composition of said layer of gate structure material along a depth of said layer of gate structure material for a slower etch rate toward a top of said layer of gate structure material that is further from said semiconductor substrate;
• C. forming said gate structure by patterning and etching said layer of gate structure material, wherein said slower etch rate toward said top of said layer of gate structure material results in a longer length toward a top of said gate structure that is further from said semiconductor substrate;
• D. implanting halo dopant toward said semiconductor substrate having said gate structure to form a drain pocket and a source pocket of said field effect transistor in said semiconductor substrate around said gate structure;
• and
• E. implanting source and drain extension dopant toward said semiconductor substrate to form a drain extension and a source extension of said field effect transistor in said semiconductor substrate around said gate structure,
• wherein said halo dopant is implanted at an angle toward said gate structure and wherein said source and drain extension dopant is implanted vertically toward said semiconductor substrate such that said drain pocket surrounds said drain extension and such that said source pocket surrounds said source extension toward a channel of said field effect transistor.

A method of fabricating a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) within a silicon substrate, the method including the steps of:

• A. depositing a layer of polysilicon on said silicon substrate;
• B. implanting nitrogen dopant into said layer of polysilicon, wherein a concentration of said nitrogen dopant varies along a depth of said layer of polysilicon, and wherein a lower concentration of said nitrogen dopant toward a top of said layer of polysilicon that is further from said silicon substrate results in a slower etch rate toward said top of said layer of polysilicon;
• C. patterning and etching said layer of polysilicon to form a gate structure of said MOSFET, wherein said slower etch rate toward said top of said layer of polysilicon results in a longer length toward a top of said gate structure that is further from said silicon substrate, and wherein said gate structure with said longer length toward said top of said gate structure has a T-shape;
• D. implanting halo dopant toward said silicon substrate having said gate structure to form a drain pocket and a source pocket of said MOSFET in said silicon substrate around said gate structure;
• E. implanting source and drain extension dopant toward said silicon substrate to form a drain extension and a source extension of said MOSFET in said silicon substrate around said gate structure,
• wherein said halo dopant is implanted at an angle toward said gate structure and wherein said source and drain extension dopant is implanted vertically toward said silicon substrate such that said drain pocket surrounds said drain extension and such that said source pocket surrounds said source extension toward a channel of said MOSFET;
• F. depositing spacer dielectric of silicon dioxide (SiO2) on exposed surfaces of said gate structure;
• G. anisotropically etching said spacer dielectric such that said spacer dielectric remains on sidewalls of said gate structure,
• wherein said longer length toward said top of said gate structure results in a substantially rectangular shaped spacer dielectric remaining on said sidewalls of said gate structure;
• H. implanting source and drain contact dopant toward said silicon substrate to form a drain contact junction and a source contact junction of said MOSFET in said silicon substrate around said spacer dielectric,
• wherein said source and drain contact dopant is implanted vertically toward said silicon substrate;
• and
• forming silicide within said gate structure and said drain contact junction and said source contact junction of said MOSFET.