US 6,306,705 B1Granted

Methods of forming capacitors, DRAM arrays, and monolithic integrated circuits

AssigneeMicron Technology, Inc.

InventorsKunal R. Parekh, John K. Zahurak, Phillip G. Wald

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Abstract

The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon. The invention also includes a capacitor comprising: a) a first capacitor plate; b) a second capacitor plate; c) a capacitor dielectric layer intermediate the first and second capacitor plates; and d) at least one of the first and second capacitor plates comprising a surface against the capacitor dielectric layer and wherein said surface comprises both doped rugged polysilicon and doped nonrugged polysilicon.

Claims6

Dependent claims

A method of forming a DRAM array comprising the following steps:

defining a first node location, a second node location and a third node location;
the second node location being electrically coupled to the first node location through a first transistor gate;
the second node location being electrically coupled to the third node location through a second transistor gate;
forming an electrically insulative layer over the node locations;
removing portions of the electrically insulative layer to form a first opening, a second opening, and a third opening;
the first, second and third openings extending to the first, second and third node locations, respectively;
forming an undoped silicon layer within the first, second and third openings to narrow the first, second and third openings;
forming a doped silicon layer within the narrowed openings;
the undoped silicon layer and the doped silicon layer within the first opening together defining a first storage node;
the undoped silicon layer and the doped silicon layer within the third opening together defining a second storage node;
the undoped silicon layer and the doped silicon layer within the second opening together defining a conductive contact;
removing a portion of the electrically insulative layer to expose sidewall surfaces of the first storage node, the second storage node and the conductive contact;
forming rugged polysilicon on the exposed sidewall surfaces;
forming a dielectric layer proximate the first and second storage nodes;
forming a cell plate layer proximate the dielectric layer;
the cell plate layer, dielectric layer and first storage node together defining a first capacitor;
the cell plate layer, dielectric layer and second storage node together defining a second capacitor;
and
forming a bitline electrically connected to the conductive contact;
the conductive contact and first capacitor together defining a first DRAM cell;
the conductive contact and second capacitor together defining a second DRAM.

18 more elements

A method of forming a DRAM array comprising the following steps:

defining a first node location, a second node location and a third node location;
the second node location being electrically coupled to the first node location through a first transistor gate;
the second node being electrically coupled to the third node location through a second transistor gate;
forming an electrically insulative layer over the node locations;
removing portions of the electrically insulative layer to form a first opening, a second opening, and a third opening;
the first, second and third openings extending to the first, second and third node locations, respectively;
forming an undoped silicon layer within the first, second and third openings to narrow the first, second and third openings;
forming a doped silicon layer within the narrowed first, second and third openings to further narrow the first, second and third openings;
forming a second undoped silicon layer within the further narrowed first, second and third openings;
the first undoped silicon layer, second undoped silicon layer and doped silicon layer within the first opening together defining a first storage node;
the first undoped silicon layer, second undoped silicon layer and doped silicon layer within the third opening together defining a second storage node;
the first undoped silicon layer, second undoped silicon layer and doped silicon layer within the second opening together defining a conductive contact;
removing a portion of the electrically insulative layer to expose sidewall surfaces of the first and second storage nodes and of the conductive contact;
forming rugged polysilicon on the exposed sidewall surfaces;
forming a dielectric layer proximate the first and second storage nodes;
forming a cell plate layer proximate the dielectric layer;
the cell plate layer, dielectric layer and first storage node together defining a first capacitor;
the cell plate layer, dielectric layer and second storage node together defining a second capacitor;
and
forming a bitline electrically connected to the conductive contact;
the conductive contact and first capacitor together defining a first DRAM cell;
and the conductive contact and second capacitor together defining a second DRAM cell.

19 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/323,554Filed 1 Jun 1999 · division
Priority: 3 Jul 1997
Granted: 23 Oct 2001
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10B 12/485
Data lines or contacts therefor: bit line contacts
H10D 1/66
Capacitors having potential barriers: conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
H10D 1/711
Electrodes: having non-planar surfaces, e.g. formed by texturisation
H10D 1/712
Having non-planar surfaces, e.g. formed by texturisation: being rough surfaces, e.g. using hemispherical grains