Power overlay chip scale packages for discrete power devices

A method of fabricating a power semiconductor device package, comprising:

• providing at least one power semiconductor device having an active major surface and an opposite major surface, with contact pads on the active major surface and a terminal contact on the opposite major surface;
• bonding an electrically and thermally conductive spacer and the opposite major surface of the at least one power semiconductor device to each other;
• providing a dielectric film having first and second sides and holes extending therethrough, the dielectric film comprising a polymeric film;
• bonding the active major surface of the at least one power semiconductor device to the second side of the dielectric film, with the contact pads in alignment with the holes;
• molding a dielectric encapsulant around the at least one semiconductor device and around at least portions of the spacer on the second side of the dielectric film to form a structure having a structure bottom opposite the dielectric film;
• forming a patterned metal layer on the first side of the dielectric film, portions of the patterned metal layer extending through the holes into electrical contact with the device contact pads;
• and
• grinding the structure from the structure bottom.

A method of fabricating a power semiconductor device package, comprising:

• providing a plurality of power semiconductor devices mounted onto electrically and thermally conductive spacers, each of the semiconductor devices having an active major surface and an opposite major surface, with contact pads on the active major surface and a terminal contact on the opposite major surface, the spacers being bonded to the opposite major surfaces of the devices;
• providing a dielectric film having first and second sides and holes extending therethrough, the dielectric film comprising a polymeric film;
• bonding the active major surfaces of the devices to the second side of the dielectric film, with the contact pads in alignment with the holes;
• molding a dielectric encapsulant around the semiconductor devices and spacers on the second side of the dielectric film to form a structure having a structure bottom opposite the dielectric film;
• grinding the structure from the structure bottom to expose the spacers and to provide a planar bottom surface;
• forming a patterned metal layer on the first side of the dielectric film, portions of the patterned metal layer extending through the holes into electrical contact with the contact pads on the active major surfaces.