US 6,304,995 B1 · Pipelined architecture to decode parallel and serial concatenated codes

Abstract

The present invention provides a method and apparatus (400) for iteratively decoding data which has been encoded with contatenated codes. The apparatus (400) includes pipelined and cascaded decoder processors (406, 430 and 436) connected to a multiple block memory device (402), through a multiplexing and data control block (404). A data decision element (437) is provided for generating decoded output data. The method includes receiving encoded data (802) while data already received is processed iteratively by decoder processors in a pipelined fashion. Decoder processors are designated to perform particular iterations (810) of an iterative decoding process which are performed simultaneously. As a decoder processor completes processing its designated iteration on a block of data, the decoder processor outputs decoding information (808) to the decoding processor designated to perform the subsequent iteration. Upon completion of all iterations for a block of data, the method includes generating output (814) consisting of the decoded data block. The method provides that once processing is complete on a data block, the memory block is made available (816) for the storing of new encoded input data.

Claims18

Dependent claims

A cascaded processor decoder for decoding encoded data, the decoder comprising:

a plurality of decoder processors, including a first cascaded decoder processor and a second cascaded decoder processor;
a metric output of said first cascaded decoder connected to a metric input of said second cascaded decoder processor;
and
a multiple-block memory connected to said decoder processors for storing encoded input data arranged in multiple data blocks.

1 more element

A cascaded processor decoder for iteratively decoding data, the decoder comprising:

a plurality of decoder processors equal in number to a predetermined number of decoding iterations, said decoder processors including at least a first cascaded decoder processor and a second cascaded decoder processor;
a metric output of said first cascaded decoder processor connected to a metric input of said second cascaded decoder processor;
a multiple-block memory comprising data blocks at least equal in number to said decoder processors;
a plurality of multiplexers connected between said data blocks and said decoder processors, said multiplexers allowing said decoder processors to selectively access any of said data blocks;
and
a data decision element for generating decoded output data, said data decision element connected to said second cascaded decoder processor.

3 more elements

Dependencies are inferred from the claim text.

Pipelined architecture to decode parallel and serial concatenated codes

Life of this patent

Pipelined architecture to decode parallel and serial concatenated codes

Life of this patent

Abstract

Claims18