Back to results
US 6,304,921 B1Granted
System for serial peripheral interface with embedded addressing circuit for providing portion of an address for peripheral devices
AssigneeMotorola, Inc.
InventorAlan M. Rooke
Life of this patent
Estimating the term…
Abstract
A microcontroller (12) provides the address bit and device data start bits for the first peripheral device (PD) in a string of PDs (20-24 or 30-34). Each PD includes a string of flipflops (72-86). If the complete address matches, then the first PD (20) shifts out the device data start bits for the next PD (22) in that string. The address bit for the next PD is provided by the pull-up or pull-down device (52) hard-wired on the SI of the next PD. The device data start bits for the next PD are provided by right-most flipflops of the previous PD. If the address bit and device data start bits match the contents of the device registers of next PD, then that next PD enables SYSCLK to shift out the contents of flipflops.
Claims18
A serial peripheral interface, comprising:
- one or more first storage elements serially coupled between an input and an output, wherein the input is coupled for receiving a data signal;
- one or more second storage elements serially coupled between an input and an output, wherein the input of the one or more second storage elements is coupled to the output of the one or more first storage elements;
- a device coupled to the input of the second storage elements for establishing a logic level at the input of the second storage elements for providing a first portion of an address for the second storage elements;
- wherein each of the one or more first storage elements and second storage elements comprises a plurality of serially connected clocked storage devices having a terminal for receiving a clock signal;
- and
- logic means within each of the one or more first storage elements and each of the one or more second storage elements for receiving the data signal and inhibiting clocking of a portion of the plurality of serially connected clocked storage devices until address verification is performed by the logic means using one or more control bits within the data signal.
3 more elements
A serial peripheral interface comprising:
- a plurality of first storage elements serially coupled between an input and an output, wherein the input is coupled for receiving a data signal, the plurality of first storage elements comprising:
- a first flipflop having a data input coupled to the input of the first storage elements, and a clock input coupled for receiving a clock signal;
- a second flipflop having a data input coupled to an output of the first flipflop, and a clock input coupled for receiving the clock signal;
- a third flipflop having a data input coupled to an output of the second flipflop, and a clock input coupled for receiving the clock signal;
- and
- a fourth flipflop having a data input coupled to an output of the third flipflop and an output coupled to the output of the first storage elements;
- a plurality of second storage elements serially coupled between an input and an output, wherein the input of the second storage elements is coupled to the output of the first storage elements;
- a logic device coupled to the input of the second storage elements for establishing a logic level at the input of the second storage elements for providing a first portion of an address for the second storage elements;
- a first logic gate having a first input coupled to the input of the first storage elements;
- a first register having an output coupled to a second input of the first logic gate;
- a first RS flipflop having a reset input coupled for receiving a chip select signal, and a set input coupled for receiving the clock signal;
- and
- a fifth flipflop having a data input coupled to an output of the first logic gate, and a clock input coupled to an output of the first RS flipflop.
10 more elements
A method of addressing cascaded serial peripheral interfaces (SPIs), comprising the steps of:
- loading an address bit and one or more start bits via a data input into first storage elements of a first SPI, while inhibiting clocking of second storage elements of the first SPI;
- determining whether the address bit and one or more start bits match an address for the first SPI;
- shifting data bits via the same data input into the first storage elements of the first SPI if the address for the first SPI matched the address bit and one or more start bits;
- shifting the address bit, the one or more start bits and the data bits along to second storage elements of the first SPI and further along to first storage elements of a second SPI if the address for the first SPI matched the address bit and one or more start bits;
- and
- receiving a first portion of an address of the second SPI hard-wired at an input of the first storage elements of the second SPI.
3 more elements
An integrated circuit for controlling a peripheral device with control data received by a serial peripheral interface comprising:
- a plurality of serially coupled storage elements addressed by receiving a first portion of an address hard-wired on an input of the storage elements and a second portion of the address in control data applied to the input of the storage elements, the storage elements comprising a plurality of series-connected flipflops, each having a data input, an output and a clock input for receiving a clock signal;
- a first logic gate having a first input coupled to the input of the storage elements;
- a first register having an output coupled to a second input of the first logic gate;
- a first RS flipflop having a reset input coupled for receiving a chip select signal, and a set input coupled for receiving the clock signal;
- and
- a fifth flipflop having a data input coupled to an output of the first logic gate, and a clock input coupled to an output of the first RS flipflop.
3 more elements
Dependencies are inferred from the claim text.