Multibit sigma-delta converters employing dynamic element matching with reduced baseband tones

An m-bit sigma-delta digital-to-analog converter, m being an integer greater than two, which comprises:

• an interpolation filter having an input for receiving a digital word with a plurality of bits, sampled at a Nyquist-rate frequency, and an output for providing an interpolated digital word, sampled at a frequency which is higher than said Nyquist-rate frequency;
• a digital sigma-delta modulator containing a digital loop filter and an m-bit truncator, which receives said interpolated digital word from said interpolation filter and provides an m-bit truncated digital word, and wherein said digital loop filter receives a summed signal of said interpolated digital word and a truncated digital output in a negative feedback sense from said truncator and generates a pre-processed signal, and said truncator truncates said pre-processed signal to provide said m-bit truncated digital word;
• an element selection logic coupled to said digital sigma-delta modulator for generating a set of control signals, S0, S1, S2, . . . , S(2m−2+k), in response to said truncated m-bit digital word from said digital sigma-delta delta modulator wherein k is a positive integer;
• an m-bit digital-to-analog converter (DAC) coupled to said element selection logic containing (2m−1+k) unit elements with component mismatches between said unit elements for providing an analog signal to a post analog filter in response to said m-bit truncated digital word from said digital sigma-delta modulator;
• wherein
• said element selection logic comprises
• a modulo-(2m−1+k) adder having an input terminal for receiving said m-bit truncated digital word from said digital sigma-delta modulator and a second pointer (PTR2), and an output terminal for providing a first pointer (PTR1), wherein the first pointer (PTR1) is a sum (t) of said m-bit truncated digital word and PTR2, and is equal to a residual value of t divided by (2m−1+k) if t is greater than (2m−2+k);
• an accumulator register coupled to said modulo-(2m−1+k) adder having an input terminal for receiving said PTR1 and an output terminal for providing said PTR2, said accumulator register latching said PTR1 for a duration of one sampling period;
• and
• a control signal generator which receives said PTR1 and PTR2 and generates said set of (2m−1+k) control signals, S0, S1, S2, . . . , S(2m−2+k), wherein
• if (PTR1−1) modulo (2m−1+k), r, is greater than PTR2, SPTR2, S(PTR2+1), . . . , Sr are 1 and the others are 0,
• if (PTR1−1) modulo (2m−1+k), r, is less than PTR2, SPTR2, S(PTR2+1), . . . , S(2m−2+k), S0, S1, . . . , Sr are 1 and the others are 0, and
• if PTR1 is equal to PTR2, all the (N−1+k) control signals, S0, S1, S2, . . . , S(2m−2+k) are 0;
• and
• said m-bit digital-to-analog converter (DAC) further comprises a switch network for selectively connecting said (2m−1+k) unit elements to a reference level or an analog ground terminal according to said set of (2m−1+k) control signals, wherein an unit element is connected to said reference level when a corresponding control signal is 1, and to said analog ground terminal when said corresponding control signal is 0.