Back to results
US 6,304,477 B1Granted
Content addressable magnetic random access memory
AssigneeMotorola, Inc.
InventorPeter K. Naji
Life of this patent
Estimating the term…
Abstract
A content addressable magnetic random access memory cell including a differentially connected pair of MTJs and comparison and match detection circuitry connected to the MTJs and including differential tag bitlines, differential tag program bitlines, an enable line, a word line, a digit line, and a match line. The match line provides an indication of a match between input data placed on the differential tag bitlines and stored data in the cell.
Claims11
A magnetic random access memory cell comprising:
- a differentially connected pair of magnetic tunnel junctions;
- and
- programming and detection circuitry connected to the differentially connected pair and including differential bitlines, differential program bitlines, an enable line, a word line, and a digit line.
A content addressable magnetic random access memory cell comprising:
- a differentially connected pair of magnetic tunnel junctions;
- and
- comparison and match detection circuitry connected to the differentially connected pair and including differential tag bitlines, differential tag program bitlines, an enable line, a word line, a digit line, and a match line, the match line providing an indication of a match between input data placed on the differential tag bitlines and stored data in the cell.
A content addressable magnetic random access memory cell comprising:
- a first magnetic tunnel junction with a first side connected through a first series connected pair of transistors to a first junction and a second magnetic tunnel junction with a first side connected through a second series connected pair of transistors to a second junction, a second side of the first magnetic tunnel junction connected to a programming bitline and a second side of the second magnetic tunnel junction connected to a programming bitline-not, and a control terminal of a first of the first series connected pair of transistors connected to an enable line and a control terminal of a first of the second series connected pair of transistors connected to the enable line;
- the first junction being coupled through a first transistor to a bitline with a control terminal of the first transistor being connected to a word line, and the second junction being coupled through a second transistor to a bitline-not with a control terminal of the second transistor being connected to the word line;
- the first junction being coupled through a first enable transistor to a power input terminal with a control terminal of the first enable transistor connected to the enable line, and the second junction being coupled through a second enable transistor to the power input terminal with a control terminal of the second enable transistor connected to the enable line;
- the first junction being coupled through a first differential transistor to the power input terminal with a control terminal of the first differential transistor connected to a control terminal of a second of the first series connected pair of transistors and to the second junction, and the second junction being coupled through a second differential transistor to the power input terminal with a control terminal of the second differential transistor connected to a control terminal of a second of the second series connected pair of transistors and to the first junction;
- and
- a first series connected pair of match transistors connected between the power input terminal and a match line with a control terminal of a first of the first pair of match transistors connected to the bitline and a control terminal of a second of the first pair of match transistors connected to the second junction, and a second series connected pair of match transistors connected between the power input terminal and the match line with a control terminal of a first of the second pair of match transistors connected to the bitline-not and a control terminal of a second of the second pair of match transistors connected to the first junction.
3 more elements
An array of memory cells connected to form a content addressable, nonvolatile memory comprising:
- a plurality of memory cells arranged in rows and columns;
- each memory cell including a differentially connected pair of magnetic tunnel junctions, and a tag bitline, a tag bitline-not, a tag program bitline, a tag program bitline-not, an enable line, a word line, a digit line, and a match line, the match line providing an indication of a match between input data placed on the differential tag bitlines and stored data in the cell;
- the tag bitline, tag bitline-not, tag program bitline, tag program bitline-not, and enable line for each memory cell in a column being coupled to the tag bitline, tag bitline-not, tag program bitline, tag program bitline-not, and enable line for each other memory cell in the column, respectively;
- the word line, digit line, and match line for each memory cell in a row being coupled to the word line, digit line, and match line for each other memory cell in the row;
- and
- match detection circuitry coupled to the match lines in each row.
3 more elements
Dependencies are inferred from the claim text.