Method and apparatus for deglitching digital to analog converters

A digital to analog converter (DAC) to convert a digital input signal into a voltage level of an analog voltage output signal, the DAC comprising:

• a plurality of digital input lines and an analog output line;
• a switched R-2R ladder coupled to the plurality of digital input lines for receiving the digital input signal, the switched R2R ladder generating an intermediate analog voltage signal in response to the digital input signal;
• a deglitch circuit coupled to the switched R-2R ladder for receiving the intermediate analog voltage signal and reducing glitch impulses thereon for generation of the analog voltage output signal on the analog output line, the deglitch circuit selectively sampling and holding the intermediate analog voltage signal for generation of the analog output signal on the analog output line substantially without glitch impulses, the selective sampling and holding of the deglitch circuit responsive to a deglitch control signal;
• a deglitch controller coupled to the plurality of digital input lines, the deglitch controller generating the deglitch control signal in response to a change in state of the digital input signal on the plurality of digital input lines to control the deglitch circuit;
• and
• the deglitch circuit including
• a sample and hold circuit coupled to the switched R-2R ladder for selectively sampling and holding the intermediate analog voltage signal after signal settling for generation of the analog output signal without primary glitch impulses in response to the deglitch control signal, and
• a glitch cancellation circuit coupled to the sample and hold circuit, the glitch cancellation circuit for generating an emulated secondary glitch impulse to cancel a secondary glitch impulse generated by the sample and hold circuit, the glitch cancellation circuit includes
• an emulation glitch generator for generation of the emulated secondary glitch impulse, and
• a differential amplifier having a negative input terminal, a positive input terminal, and an output terminal coupled to the analog output line, the differential amplifier having the negative input terminal coupled to the emulation glitch generator for receiving the emulated secondary glitch impulse and having the positive input terminal coupled to the sample and hold circuit, the differential amplifier substantially rejecting the secondary glitch impulse generated by the sample and hold circuit and generating the analog output signal substantially without glitch impulses on the analog output line.

A digital to analog converter (DAC) to convert a digital input signal into a voltage level of an analog voltage output signal, the DAC comprising:

• a plurality of digital input lines and an analog output line;
• a switched R-2R ladder coupled to the plurality of digital input lines for receiving the digital input signal, the switched R2R ladder generating an intermediate analog voltage signal in response to the digital input signal;
• a deglitch circuit coupled to the switched R-2R ladder for receiving the intermediate analog voltage signal and reducing glitch impulses thereon for generation of the analog voltage output signal on the analog output line, the deglitch circuit selectively sampling and holding the intermediate analog voltage signal for generation of the analog output signal on the analog output line substantially without glitch impulses, the selective sampling and holding of the deglitch circuit responsive to a deglitch control signal;
• and
• a synchronous deglitch controller coupled to the plurality of digital input lines, the synchronous deglitch controller generating the deglitch control signal responsive to a change in state of the digital input signal on the plurality of digital input lines and synchronously responsive to a digital input load pulse,
• the deglitch controller includes
• a latch for latching the digital input signal in response to the digital input load pulse,
• a one shot pulse generator for generating a one shot pulse responsive to the digital input load pulse, and
• an inverter for inverting the one shot pulse,
• such that the deglitch control signal is generated responsive to the one shot pulse causing the deglitch circuit to stop sampling and start holding the intermediate analog voltage signal.

A digital to analog converter (DAC) to convert a digital input signal into a voltage level of an analog voltage output signal, the DAC comprises:

• a plurality of digital input lines and an analog output line;
• a switched R-2R ladder coupled to the plurality of digital input lines for receiving the digital input signal, the switched R2R ladder generating an intermediate analog voltage signal in response to the digital input signal;
• a deglitch circuit coupled to the switched R-2R ladder for receiving the intermediate analog voltage signal and reducing glitch impulses thereon for generation of the analog voltage output signal on the analog output line, the deglitch circuit selectively sampling and holding the intermediate analog voltage signal for generation of the analog output signal on the analog output line substantially without glitch impulses, the selective sampling and holding of the deglitch circuit responsive to a deglitch control signal;
• and
• an asynchronous deglitch controller to control the deglitch circuit, the asynchronous deglitch controller coupled to the plurality of digital input lines to generate the deglitch control signal in response to a change in state of the digital input signal, the asynchronous deglitch controller includes
• a delay element for preserving a prior state of the digital input signal,
• an exclusive-OR gate coupled to the delay element and a digital input line, the exclusive-OR gate for receiving and comparing a new state of the digital input signal and the prior state of the digital input signal to determine a change in state or no change in state of the digital input signal, and,
• a one shot pulse generator coupled to the exclusive-OR gate for generating the deglitch control signal to stop sampling and start holding the intermediate analog voltage signal in response to the exclusive-OR gate determining a change in state in the digital input signal.

A method of converting a digital signal into an analog signal output substantially without glitch impulses, comprising:

• a) providing a switched R-2R ladder generating an analog signal responsive to the digital signal;
• b) sampling the analog signal prior to a change in state of the digital signal;
• c) detecting for a change in state of the digital signal;
• d) stopping the sampling of the analog signal upon detecting a change in state of the digital signal and holding the analog level of the analog signal to avoid sampling primary glitch impulses;
• and
• e) after a predetermined time, resampling the analog signal.

An automated tester for testing electronic circuits, the tester comprising:

• a computer for receiving and executing test programs for testing electronic circuits, the test programs causing analog voltage levels to be applied to the electronic circuits over a plurality of periodic intervals, test programs further causing analog voltage levels provided on outputs from the electronic circuits to be compared with expected data to generate a pass or fail for electronic circuits being tested;
• and,
• a test station for coupling to an electronic circuit for testing, the test station coupled to the computer for receiving instructions and input digital signals to cause analog voltage levels to be applied to the electronic circuits over the plurality of periodic intervals and for causing analog voltage levels provided on outputs of the electronic circuits to be converted into digital form for communication to the computer for comparison with expected data, the test station comprising,
• a plurality of digital to analog converters for generation of analog voltage levels for coupling to inputs of the electronic circuits over the plurality of periodic intervals, each digital to analog converter of the test station comprising,
• a switched R-2R ladder for generating an intermediate analog voltage signal in response to the input digital signals;
• a deglitch circuit coupled to the switched R-2R ladder for receiving the intermediate analog voltage signal and reducing glitch impulses thereon for generation of the analog levels, the deglitch circuit selectively sampling and holding the intermediate analog voltage signal for generation of the analog voltage levels to be applied to the electronic circuits, the analog voltage levels substantially without glitch impulses, the selective sampling and holding of the deglitch circuit responsive to a deglitch control signal;
• and
• a deglitch controller for generating the deglitch control signal in response to a change in state of the input digital signals to control the deglitch circuit.

An automated tester for testing electronic circuits, the tester comprising:

• a computer for receiving and executing test programs for testing electronic circuits, the test programs causing analog voltage levels to be applied to the electronic circuits over a plurality of periodic intervals, test programs further causing analog voltage levels provided on outputs from the electronic circuits to be compared with expected data to generate a pass or fail for electronic circuits being tested;
• and,
• a test station to coupling to an electronic circuit for testing, the test station coupled to the computer to receive instructions and input digital signals to cause analog voltage levels to be applied to the electronic circuits over the plurality of periodic intervals and to cause analog voltage levels provided on outputs of the electronic circuits to be converted into digital form for communication to the computer for comparison with expected data, the test station comprising,
• a plurality of digital to analog converters to generate analog voltage levels for coupling to inputs of the electronic circuits over the plurality of periodic intervals, each digital to analog converter of the test station including,
• a switched R-2R ladder to generate an intermediate analog voltage signal in response to the input digital signals,
• a deglitch circuit coupled to the switched R-2R ladder to receive the intermediate analog voltage signal and to reduce glitch impulses thereon for generation of the analog levels, the deglitch circuit to selectively sample and hold the intermediate analog voltage signal to generate the analog voltage levels to be applied to the electronic circuits, the analog voltage levels substantially without glitch impulses, the selective sampling and holding of the deglitch circuit responsive to a deglitch control signal, the deglitch circuit including
• a sample and hold circuit coupled to the switched R-2R ladder to selectively sample and hold the intermediate analog voltage signal after signal settling to generate the analog voltage levels in response to the deglitch control signal,
• a glitch cancellation circuit coupled to the sample and hold circuit, the glitch cancellation circuit to generate an emulated secondary glitch impulse to cancel a secondary glitch impulse generated by the sample and hold circuit, the glitch cancellation circuit includes
• an emulation glitch generator to generate the emulated secondary glitch impulse, and
• a differential amplifier having a negative input terminal, a positive input terminal, and an output terminal, the differential amplifier having the negative input terminal coupled to the emulation glitch generator to receive the emulated secondary glitch impulse and having the positive input terminal coupled to the sample and hold circuit, the differential amplifier to reject the secondary glitch impulse generated by the sample and hold circuit and to generate the analog voltage levels substantially without glitch impulses, and
• a deglitch controller to generate the deglitch control signal in response to a change in state of the input digital signals to control the deglitch circuit.

An automated tester for testing electronic circuits, the tester comprising:

• a computer for receiving and executing test programs for testing electronic circuits, the test programs causing analog voltage levels to be applied to the electronic circuits over a plurality of periodic intervals, test programs further causing analog voltage levels provided on outputs from the electronic circuits to be compared with expected data to generate a pass or fail for electronic circuits being tested;
• and,
• a test station to coupling to an electronic circuit for testing, the test station coupled to the computer to receive instructions and input digital signals to cause analog voltage levels to be applied to the electronic circuits over the plurality of periodic intervals and to cause analog voltage levels provided on outputs of the electronic circuits to be converted into digital form for communication to the computer for comparison with expected data, the test station comprising,
• a plurality of digital to analog converters to generate analog voltage levels for coupling to inputs of the electronic circuits over the plurality of periodic intervals, each digital to analog converter of the test station including,
• a switched R-2R ladder to generate an intermediate analog voltage signal in response to the input digital signals,
• a deglitch circuit coupled to the switched R-2R ladder to receive the intermediate analog voltage signal and to reduce glitch impulses thereon for generation of the analog levels, the deglitch circuit to selectively sample and hold the intermediate analog voltage signal to generate the analog voltage levels to be applied to the electronic circuits, the analog voltage levels substantially without glitch impulses, the selective sampling and holding of the deglitch circuit responsive to a deglitch control signal, and
• a synchronous deglitch controller to control the deglitch circuit in synchronous with a digital input load pulse, the synchronous deglitch controller to generate the deglitch control signal in response to a change in state of the input digital signals and in synchronous response to the digital input load pulse, the synchronous deglitch controller includes
• a latch to latch a prior state of the input digital signals,
• a one shot pulse generator to generate a one shot pulse responsive to the digital input load pulse, and
• an inverter to invert the one shot pulse, whereby the deglitch control signal is generated responsive to the one shot pulse causing the deglitch circuit to stop sampling and start holding the intermediate analog voltage signal.

A deglitch circuit for a digital to analog converter (DAC), the deglitch circuit comprising:

• a sample and hold circuit coupled to an analog output of a DAC, the sample and hold circuit to selectively sample and hold an analog voltage signal from the analog output after signal settling to generate an analog output signal without primary glitch impulses, the selective sampling and holding of the sample and hold circuit responsive to a change in state of a digital input signal coupled into the DAC for conversion to an analog signal, the sample and hold circuit generating a secondary glitch impulse in the selective sampling and holding;
• an emulation glitch generator to generate an emulated secondary glitch impulse;
• and
• a differential amplifier having a negative input terminal, a positive input terminal, and an output terminal, the differential amplifier having the negative input terminal coupled to the emulation glitch generator to receive the emulated secondary glitch impulse and having the positive input terminal coupled to the sample and hold circuit, the differential amplifier to reject the secondary glitch impulse generated by the sample and hold circuit and to generate the analog output signal substantially without glitch impulses.

A deglitch circuit for a digital to analog converter (DAC), the deglitch circuit comprising:

• a sample and hold circuit coupled to an intermediate analog output of a DAC, the sample and hold circuit to selectively sample and hold an analog voltage signal from the intermediate analog output after signal settling to generate an analog output signal without primary glitch impulses, the selective sampling and holding of the sample and hold circuit responsive to a deglitch control signal, the sample and hold circuit to generate a secondary glitch impulse in response to a change in state of the deglitch control signal;
• a first analog switch to generate an emulated secondary glitch impulse in response to the change in state of the deglitch control signal, the first analog switch having a first terminal, a second terminal and at least one control terminal, the at least one control terminal coupled to the deglitch control signal;
• a differential amplifier having a negative input terminal, a positive input terminal, and an output terminal, the differential amplifier having the negative input terminal coupled to the second terminal of the first analog switch and the positive input terminal coupled to the sample and hold circuit;
• a first resistor having one end coupled to the output terminal of the differential amplifier and another end coupled to the first terminal of the first analog switch;
• a second resistor having one end coupled to the first terminal of the first analog switch and the another end of the first resistor and the second resistor having another end coupled to ground;
• a first capacitor having one end coupled to the output terminal of the differential amplifier and another end coupled to the negative input terminal of the differential amplifier and the second terminal of the first analog switch;
• and
• a second capacitor having one end coupled to the negative input terminal of the differential amplifier and the second terminal of the first analog switch and another end coupled to ground.

A digital to analog converter (DAC), comprising:

• a switching means to generate an intermediate analog signal responsive to a digital input signal;
• a sample and hold means to sample the intermediate analog signal prior to a change in state in the digital input signal and to stop sampling of the intermediate analog signal and hold the analog level of the intermediate analog signal to avoid sampling primary glitch impulses in response to a deglitch signal;
• and
• a detecting means to detect a change in the digital input signal and generate the deglitch signal in response thereto.

A digital to analog converter (DAC) to convert a digital input signal into a voltage level of an analog voltage output signal, the DAC comprising:

• a digital input terminal and an analog output terminal;
• a switching means coupled to the digital input terminal to receive the digital input signal, the switching means to generate an intermediate analog voltage signal in response to the digital input signal;
• a deglitching means coupled to the switching means to receive the intermediate analog voltage signal and to reduce glitch impulses thereon, the deglitching means selectively sampling and holding the intermediate analog voltage signal to generate a sampled intermediate analog voltage signal, the selective sampling and holding of the deglitching means responsive to a deglitch control signal;
• and
• a controlling means coupled to the digital input terminal, the controlling means to generate the deglitch control signal in response to a change in the digital input signal at the digital input terminal.