Complementary input self-biased differential amplifier with gain compensation

A complementary input self-biased differential amplifier comprising:

• a first differential amplifier having an N-channel input transistor pair, a P-channel load transistor pair, and a first current source, the N-channel input transistor pair being coupled to a differential input node, and the first current source having a bias input node coupled to a self-bias node;
• a second differential amplifier having a P-channel input transistor pair, an N-channel load transistor pair, and a second current source, the P-channel input transistor pair being coupled to the differential input node in parallel with the N-channel input transistor pair, and the second current source having a bias input node coupled to the self-bias node;
• and
• a gain compensation transistor pair having gates coupled to the self-bias node;
• wherein the gain compensation transistor pair comprises a pair of N-channel transistors, each having a source and drain coupled in parallel with a source and drain of a corresponding one of the N-channel input transistor pair.

A complementary input self-biased differential amplifier comprising:

• an N-channel differential input transistor stage configured to be responsive to an input signal on an input node and a reference signal on a reference node, the N-channel differential input transistor stage being coupled between a first current source and a pair of P-channel load transistors;
• a P-channel differential input transistor stage configured to be responsive to the input signal on the input node and the reference signal on the reference node, the P-channel differential input transistor stage being coupled between a second current source and a pair of N-channel load transistors;
• a differential output comprising a first node fed back into the self-biased differential amplifier as a self-bias node, and all amplifier output node configured to drive a load external to the self-biased differential amplifier;
• at least one gain compensating transistor having a gate coupled to the self-bias node, and a source and drain coupled in parallel with one of the differential input transistor stages;
• a first pair of series connected transistors coupled between a first transistor of the pair of P-channel load transistors and a first transistor of the pair of N-channel load transistors, a junction formed between the first pair of series connected transistors being the self-bias node;
• and
• a second pair of series connected transistors coupled between a second transistor of the pair of P-channel load transistors and a second transistor of the pair of N-channel load transistors, a junction formed between the second pair of series connected transistors being the amplifier output node.

A complementary input self-biased differential amplifier comprising:

• a first differential amplifier having differential input nodes and differential output nodes, the differential input nodes being coupled to a first differential pair of transistors;
• a second differential amplifier having differential input nodes in common with the first differential amplifier, and having differential output nodes, the differential input nodes being coupled to a second differential pair of transistors;
• a plurality of output impedance increasing transistors coupled between the differential output nodes of the first differential amplifier and the differential output nodes of the second differential amplifier to create a bias node and an amplifier output node;
• and
• at least one gain compensating transistor coupled in parallel to one transistor of the first differential pair of transistors, the at least one gain compensating transistor having a gate coupled to the bias node;
• wherein the first differential pair of transistors comprises;
• a first reference input transistor;
• a first select transistor in series with the first reference input transistor, the first select transistors having a gate coupled to a first control node;
• a second reference input transistor;
• and
• a second select transistor in series with the second reference input transistor, the second select transistor having a gate coupled to a second control node, such that when signals on the first and second control nodes have opposite polarity, one of the first and second select transistors is on, and the other is off.