Recording head and recording apparatus using the same
AssigneeCanon Kabushiki Kaisha
InventorsYoshiyuki Imanaka, Masami Kasamoto, Tatsuo Furukawa, Toshihiro Mori, Teruo Ozaki, Hidenori Watanabe, Muga Mochizuki
Life of this patent
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Abstract
Upon executing printing by latching an input digital image signal temporarily stored in a shift register (502) by a latch circuit (501), and energizing and driving a heater (401) using a power transistor (410) using an nMOSFET on the basis of the latched image signal, a voltage converter (111) boosts a voltage representing the ON state of the latched digital signal, and applies the boosted voltage to the power transistor (410).
Claims71
A recording head comprising:
- a heater corresponding to a print element;
- a MOS power transistor connected to said heater in electrical series for energizing and driving said heater;
- a MOS logic circuit for driving said MOS power transistor;
- and
- a voltage converter for converting a voltage amplitude of a signal output from said MOS logic circuit into a higher voltage amplitude, and applying a signal with the converted amplitude to a gate electrode of said MOS power transistor.
A substrate for driving a recording head, said substrate comprising:
- a heater corresponding to a print element;
- a MOS power transistor connected to said heater in electrical series for energizing and driving said heater;
- a MOS logic circuit for driving said MOS power transistor;
- and
- a voltage converter for converting a voltage amplitude of a signal output from said MOS logic circuit into a higher voltage amplitude, and applying a signal with the converted amplitude to a gate electrode of said MOS power transistor.
A recording head comprising a substrate, said substrate comprising:
- a heater corresponding to a print element;
- a MOS power transistor connected to said heater in electrical series for energizing and driving said heater;
- a MOS logic circuit for driving said MOS power transistor;
- and
- a voltage converter for converting a voltage amplitude of a signal output from said MOS logic circuit into a higher voltage amplitude, and applying a signal with the converted amplitude to a gate electrode of said MOS power transistor.
Dependencies are inferred from the claim text.