Architecture and method for inverse quantization of discrete cosine transform coefficients in MPEG decoders
AssigneeLSI Logic Corporation
InventorsTai Jing, Surya Varanasi
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AssigneeLSI Logic Corporation
InventorsTai Jing, Surya Varanasi
Estimating the term…
An inverse quantizer is provided with a reduced bit-width. In one embodiment, the inverse quantizer receives quantized DCT coefficients in sign+magnitude form with 1+11 bits of resolution, and produces reconstructed DCT coefficients with 1+11 bits of resolution. Although this is less than the theoretical minimum bit-width required to represent the entire reconstructed DCT coefficient range [−2048, 2047] mandated by the MPEG standard, certain IDCT implementations will maintain IEEE compliance when the −2048 value is replaced with −2047. (An example of one such implementation is provided in a co-pending application.) This reduces the range to [−2047, 2047]. In one embodiment, the inverse quantizer includes a dead-zone expander, a quantization multiplier, a mismatch controller, and a bit-width reducer. The dead-zone expander receives quantized coefficients with 1+11 bits of resolution, doubles them, and then increases their magnitude by one. The quantization multiplier multiplies the result by a 15 bit quantization matrix scale factor to produce reconstructed DCT coefficients. The mismatch controller modifies least significant bits of DCT coefficients according to the MPEG standard and limits the range of values for the DCT coefficients. Finally, the bit-width reducer converts the DCT coefficient representation to 1+11 bits.
A video decoder which satisfies IEEE Standard 1180-1990 while having a reduced implementation complexity, wherein the video decoder comprises:
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