US 6,301,153 B1 · Nonvolatile semiconductor memory device

Abstract

A memory cell array includes first and second memory cell groups which are simultaneously selected at the time of erasing. A first bit line is connected to the first memory cell group and a second bit line is connected to the second memory cell group. The first and second bit lines are commonly connected to a data circuit having a latch circuit. First data read from the first memory cell group at the time of erase verify read for the first memory cell group is input to the data circuit and second data read from the second memory cell group at the time of erase verify read for the second memory cell group is input to the data circuit. The data circuit latches data indicating that the erasing operation is completed into the latch circuit when both of the first and second data items indicate that the erasing states of the memory cells are sufficient and latches data indicating that the erasing operation is effected again into the latch circuit when at least one of the first and second data items indicates that the erasing state of the memory cell is insufficient.

Claims34

Dependent claims

A verify read method comprising the steps of:

performing an erasing step of a first memory cell and a second memory cell;
reading out a first data of the first memory cell;
transferring the first data from the first memory cell to a first latch circuit through a first bit line and a common node;
reading out a second data of the second memory cell;
and
transferring the second data front the second memory cell to a second latch circuit through a second bit line and the common node, the second bit line being adjacent to the first bit line.

3 more elements

Dependencies are inferred from the claim text.

Nonvolatile semiconductor memory device

Life of this patent

Nonvolatile semiconductor memory device

Life of this patent

Abstract

Claims34