# US 6,298,420 B1 · Coherent variable length reads from system memory

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- Number: US 6,298,420 B1
- Document ID: US6298420B1
- Status: Granted
- Kind: B1
- Application number: 09/567,139
- Filed: 2000-05-08
- Granted: 2001-10-02
- Earliest claimed: 1998-01-26
- Assignees: Intel Corporation
- Inventors: Suresh Chittor; Chih-Cheh Chen; Sin Sim Tan; Jonathan Nick Spitz
- Web page: https://patentgrep.com/patent/US6298420B1

## CPC

- G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means
- G06F 13/1642: {with request queuing}
- G06F 12/0886: Variable-length word access
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Method and apparatus for processing serial bus read requests in a memory controller when the memory controller interfaces to both a pipelined bus and a serial bus. According to the method, the read request message is received and is split into several atomic transactions. The atomic transactions are issued on the pipelined bus. Data related to the several atomic transactions is stored in a queue. The requested data is read from the queue and placed in a response message on the serial bus.

## Claims

### Claim 1

In a memory controller directly connected to a system memory, to a pipelined bus and to a serial bus, the pipelined bus characterized by a cache line width, a method of processing a read request message received from the serial bus that implicates data within a single cache line, comprising:
receiving the read request message,
issuing a read invalidate transaction on the pipelined bus identifying a cache line of the requested data,
retrieving data of the cache line from the system memory to a queue,
reading the requested data from the queue, and
placing a response message on the serial bus, the response message containing the requested data.

### Claim 2 (depends on 1)

The method of claim 1, further comprising, if cache coherency signaling associated with the read invalidate transaction indicates modified data:
terminating the retrieval of data from the system memory, and instead
retrieving data of the cache line from the pipelined bus to the queue.