# US 6,298,413 B1 · Apparatus for controlling refresh of a multibank memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,298,413 B1 - Document ID: US6298413B1 - Status: Granted - Kind: B1 - Application number: 09/196,571 - Filed: 1998-11-19 - Granted: 2001-10-02 - Earliest claimed: 1998-11-19 - Assignees: Micron Technology, Inc. - Inventors: Leonard E. Christenson - Web page: https://patentgrep.com/patent/US6298413B1 ## CPC - G11C 11/406: Management or control of the refreshing or charge-regeneration cycles - G06F 13/1636: {using refresh} - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus is described for controlling refresh of a multibank DRAM. A memory controller includes refresh request circuitry having a refresh counter and address incrementer. The refresh counter produces a refresh request signal, with the address incrementer producing an associated refresh address. The refresh request and address are handled much like a memory read operation, with the associated read data being ignored. In one implementation, the refresh request is given priority over any other pending memory access request. Refresh operations are initiated without first waiting for all DRAM banks to be precharged, thereby avoiding the significant time penalties associated with the prior art. ## Claims ### Claim 1 A computer system, comprising: a processor; a memory operable to store data having a plurality of memory banks; and a memory controller coupling the processor with the memory, the memory controller having a request arbiter circuit receiving pending data transfer requests and refresh requests, the request arbiter circuit operable to determine the order in which to selectively transmit the refresh or one of the pending data transfer; a request queue circuit coupled to the request queue circuit, the request queue circuit storing a plurality of pending data transfer requests and providing data transfer request to the request; a refresh request circuit coupled to the request arbiter circuit to provide refresh requests thereto; and a state machine circuit coupled to the request arbiter circuit to receive the selected refresh request or pending data transfer request and to produce a plurality of control signals to initiate a refresh operation direction to a first memory bank while a data transfer operation is being executed in a second memory bank. ### Claim 2 (depends on 1) A computer system according to claim 1 wherein the memory controller includes: a timing circuit operable to substantially determine the time at which the refresh operation is initiated; and an address circuit operable to provide an address of a location in the first bank to which the refresh operation is directed. ### Claim 3 (depends on 1) A computer system according to claim 1 wherein the refresh request provided by the refresh request circuit includes an address of a location in the first bank to which the refresh operation is directed. ### Claim 4 (depends on 1) A computer system according to claim 1 wherein the memory is an SDRAM. ### Claim 5 (depends on 1) A computer system according to claim 1 wherein the memory is an SLDRAM. ### Claim 6 A memory controller for controlling operations of a memory having a plurality of banks, comprising: a request buffer operable to store a pending data transfer request; a refresh requester operable to produce a refresh request; and a control state machine coupled with the request buffer and with the refresh requester, the control state machine operable to receive the data transfer request and to responsively apply a first plurality of control signals to the memory to initiate data transfer operations thereof, the control state machine also operable to receive the refresh request and to responsively apply a second plurality of control signals to the memory to initiate refresh operations thereof, the control state machine initiating refresh operations addressed to a first of the banks while data transfer operations are being executed in a second of the banks; a request arbiter coupling the control state machine with the request buffer and with the refresh requester, the arbiter circuitry operable to determine which of the second data transfer and refresh requests to first provide to the control state machine. ### Claim 7 (depends on 6) A memory controller according to claim 6 wherein the data transfer request is a first data transfer request, and wherein the request buffer is operable to also store a second data transfer request. ### Claim 8 (depends on 6) A memory controller according to claim 6 wherein the refresh request produced by the refresh requester includes an address of a location in the first bank to which the refresh operations are addressed. ### Claim 9 (depends on 6) A memory controller according to claim 6 wherein the refresh requester includes a timing circuit operable to substantially determine the time at which the refresh operations are initiated. ### Claim 10 (depends on 6) A memory controller according to claim 6 wherein the refresh requester includes an address circuit operable to generate an address of a location in the first bank to which the refresh operations are addressed. ### Claim 11 A memory controller for controlling operations of a multibank memory that registers commands and requires a minimum command time interval between successive registration of commands addressed to the same bank, the memory controller comprising: request buffer circuitry operable to store a data transfer request; refresh request circuitry operable to produce a refresh request; and control state circuitry coupled with the request buffer circuitry and with the refresh request circuitry, the control state circuitry operable to receive the data transfer request and to responsively register a data transfer command in the memory, the control state circuitry also operable to receive the refresh request and to responsively register a refresh command in the memory prior to elapse of the command time interval from registration of the data transfer command to initiate a refresh operation directed to a first memory bank while a data transfer operation is being executed in a second memory bank. ### Claim 12 (depends on 11) A memory controller according to claim 11 wherein the data transfer request is a first data transfer request, wherein the data transfer command is a first data transfer command, and wherein the request buffer circuitry is operable to also store a second data transfer request, the control state circuitry being operable to receive the second data transfer request and responsively register a second data transfer command in the memory prior to elapse of the command time interval from registration of the first data transfer command. ### Claim 13 (depends on 12) A memory controller according to claim 12, further comprising arbiter circuitry coupling the control state circuitry with the request buffer circuitry and with the refresh request circuitry, the arbiter circuitry operable to determine which of the second data transfer and refresh requests to first provide to the control state circuitry. ### Claim 14 (depends on 11) A memory controller according to claim 11 wherein the refresh request produced by the refresh request circuitry includes a memory address to which the refresh command is directed. ### Claim 15 (depends on 11) A memory controller according to claim 11 wherein the refresh request circuitry includes a timing circuit operable to determine the time at which the refresh request is produced. ### Claim 16 (depends on 11) A memory controller according to claim 11 wherein the refresh request circuitry includes an address circuit operable to generate a memory address to which the refresh command is directed. ### Claim 17 A memory controller for controlling operations of a memory having a plurality of banks, comprising: a request buffer operable to store a pending data transfer request; a refresh requester operable to produce a refresh request; a request arbiter coupled with the request buffer and with the refresh requester to receive the data transfer and refresh requests, the arbiter circuitry operable to determine the order in which the data transfer requests and the refresh requests are executed; and a control state machine coupled with the request arbiter, the control state machine operable to receive the data transfer request from the request arbiter and to responsively apply a first plurality of control signals to the memory to initiate data transfer operations thereof, the control state machine also operable to receive the refresh request from the request arbiter and to responsively apply a second plurality of control signals to the memory to initiate refresh operations thereof, the control state machine initiating refresh operations addressed to a first of the banks while data transfer operations are being executed in a second of the banks. ### Claim 18 (depends on 17) A memory controller according to claim 17 wherein the data transfer request is a first data transfer request, and wherein the request buffer is operable to also store a second data transfer request. ### Claim 19 (depends on 17) A memory controller according to claim 17 wherein the refresh request produced by the refresh requester includes an address of a location in the first bank to which the refresh operations are addressed. ### Claim 20 (depends on 17) A memory controller according to claim 17 wherein the refresh requester includes a timing circuit operable to substantially determine the time at which the refresh operations are initiated. ### Claim 21 (depends on 17) A memory controller according to claim 17 wherein the refresh requester includes an address circuit operable to generate an address of a location in the first bank to which the refresh operations are addressed. ### Claim 22 A memory controller for controlling operations of a multibank memory that registers commands and requires a minimum command time interval between successive registration of commands aessed to the same bank, the memory controller comprising: request buffer circuitry operable to store a data transfer request; refresh request circuitry operable to produce a refresh request; control static circuitry operable to receive the data transfer request and to responsively register a data transfer command in the memory, the control state circuitry also operable to receive the refresh request and to responsively register a refresh command in the memory prior to elapse of the command time interval from registration of the data transfer command; and arbiter circuitry coupling the control state circuitry with the request buffer circuitry and with the refresh request circuitry to provide the control state circuitry data transfer requests and refresh request, the arbiter circuitry operable to determine the order in which to provide data transfer and refresh requests to the control state circuitry to initiate a refresh operation directed to a first memory bank while a data transfer operation is being executed in a second memory bank. ### Claim 23 (depends on 22) A memory controller according to claim 22 wherein the data transfer request is a first data transfer request, wherein the data transfer command is a first data transfer command, and wherein the request buffer circuitry is operable to also store a second data transfer request, the control state circuitry being operable to receive the second data transfer request and responsively register a second data transfer command in the memory prior to elapse of the command time interval from registration of the first data transfer command. ### Claim 24 (depends on 22) A memory controller according to claim 22 wherein the refresh request produced by the refresh request circuitry includes a memory address to which the refresh command is directed. ### Claim 25 (depends on 22) A memory controller according to claim 22 wherein the refresh request circuitry includes a timing circuit operable to determine the time at which the refresh request is produced. ### Claim 26 (depends on 22) A memory controller according to claim 22 wherein the refresh request circuitry includes an address circuit operable to generate a memory address to which the refresh command is directed.