Concurrent programming apparatus with status detection capability

Abstract

A computer controlled group of programmer sites are provided to burn in or enter operating code into various types of programmable electronic devices, such as programmable memories, programmable logic devices (or PLD's), field programmable gate arrays (or FPGA's), and the like. The programmer sites are connected to a central controller and operate under control of the central controller, typically personal computer. Each programmer site includes its own computer processor or CPU. Initially for a production run of a particular type of device, one of the programmer sites serves as a master site. At the master site, an optimized control sequence for the device is developed in conjunction with the central controller. Once this is achieved, the optimal sequence is broadcast to all programmer sites connected to the central controller. Thereafter, each programmer site, including the former master site, operates autonomously to program the devices independently of the status of the other sites, while the central computer scans each of the network sites in a timed sequence and provides monitoring and reporting functions.

Dependencies are inferred from the claim text.