# US 6,298,104 B1 · Clock recovery circuit

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- Number: US 6,298,104 B1
- Document ID: US6298104B1
- Status: Granted
- Kind: B1
- Application number: 09/131,442
- Filed: 1998-08-10
- Granted: 2001-10-02
- Earliest claimed: 1997-08-12
- Assignees: NEC Corporation
- Inventors: Takanori Saeki
- Web page: https://patentgrep.com/patent/US6298104B1

## CPC

- H04L 7/027: extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
- H04L 7/0276: {Self-sustaining, e.g. by tuned delay line and a feedback path to a logical gate}
- H04L 7/0337: {Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A clock recovery circuit enables a time for obtaining synchronized state of one pair of gate voltage-controlled oscillator to be shortened in a phase locked loop (PLL). In the clock recovery circuit, data is inputted to a pulse-duration generating circuit, before generating pulse width less than ¼ minimum data cycle from H of pulse, L of pulse, or both edges of H and L, thus the pulse is outputted both to a latched-circuit and a synchronous delay circuit. The synchronous delay circuit causes a delay time in proportion to data cycle to be generated at both edges of pulse or edge of two pulses, thus the delay time is maintained. An output pulse from a delay circuit is outputted both to a delay circuit and a latched-circuit by way of clock from the pulse synthesis circuit. The latched-circuit causes the data as an input to be latched by the clock from the pulse synthesis circuit, thus outputting regenerative data in company with the clock.

## Claims

### Claim 1

A clock recovery circuit comprising:
a synchronous delay circuit which sets a delay time equivalent to a minimum data pitch of an input data, and which maintains said delay time;
a pulse synthesis circuit which generates a clock from a data edge with a pulse from said synchronous delay circuit as an input; and
a latched-circuit which latches data by using the clock from said pulse synthesis circuit, thus generating regenerative data.

### Claim 2 (depends on 1)

A clock recovery circuit as claimed in claim 1, wherein said synchronous delay circuit sets a delay time equivalent to a minimum data pitch of data from both edges of said input data.

### Claim 3 (depends on 1)

A clock recovery circuit as claimed in claim 1, wherein said synchronous delay circuit sets a delay time equivalent to a minimum data pitch of data from two successive input data.

### Claim 4 (depends on 1)

A clock recovery circuit as claimed in claim 1, wherein a delay time set by said synchronous delay circuit. is equivalent to width of 1-bit of the data.

### Claim 5

A data processing method of a clock recovery circuit which comprises a synchronous delay circuit, a pulse synthesis circuit, and a latched-circuit comprising the steps of:
setting a delay time equivalent to a minimum data pitch of an input data, and maintaining said delay time;
generating a clock from a data edge with a pulse from said synchronous delay circuit as an input; and
latching data by using the clock from said pulse synthesis circuit, thus generating regenerative data.