# US 6,297,994 B1 · Single electron MOSFET memory device and method

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- Number: US 6,297,994 B1
- Document ID: US6297994B1
- Status: Granted
- Kind: B1
- Application number: 09/619,177
- Filed: 2000-07-19
- Granted: 2001-10-02
- Earliest claimed: 1998-08-26
- Assignees: Micron Technology, Inc.
- Inventors: Kie Ahn; Leonard Forbes
- Web page: https://patentgrep.com/patent/US6297994B1

## CPC

- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G11C 11/34: using semiconductor devices
- G11C 11/40: using transistors
- G11C 11/404: with one charge-transfer gate, e.g. MOS transistor, per cell
- G11C 16/3436: {Arrangements for verifying correct programming or erasure}
- G11C 16/3445: {Circuits or methods to verify correct erasure of nonvolatile memory cells}
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10D 30/688: {programmed by two single electrons}
- G11C 2216/08: Nonvolatile memory wherein data storage is accomplished by storing relatively few electrons in the storage layer, i.e. single electron memory
- Y10S 438/962: Quantum dots and lines
- Y10S 977/937: Single electron transistor
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A memory device and related methods are described. The memory device includes a plurality of cells, each cell including a MOSFET having a source coupled to a first end of a channel, a drain coupled to a second end of the channel, a gate formed on a gate insulator and extending from the source to the drain and a plurality of conductive islands, each surrounded by an insulator, formed in the channel. The islands have a maximum dimension of three nanometers. The surrounding insulator has a thickness of between five and twenty nanometers. Each island and surrounding insulator is formed in a pore extending into the channel. As a result, the memory cells are able to provide consistent, externally observable changes in response to the presence or absence of a single electron on the island.

## Claims

### Claim 1

A method of operating a selected memory cell comprising:
applying a positive voltage to a gate of a MOSFET comprising the selected memory cell to form a channel;
storing data represented by presence or absence of one or more electrons in an island formed from conductive material in an anodically-defined pore in the channel, the island insulated from the channel;
accessing the selected memory cell at a time after the act of storing data;
sampling an electrical parameter manifested by the selected memory cell in response to a stimulus; and
determining when one or more electrons are stored in the island in the selected memory cell from the sample of the electrical parameter.

### Claim 2 (depends on 1)

The method of claim 1 wherein the act of storing data comprises:
applying a voltage pulse across a drain and a source coupled to the channel to write data to the selected memory cell;
reading data from the selected memory cell;
comparing the read data to the data written to the selected memory cell; and
iterating the acts of applying a voltage pulse, reading data and comparing the read and write data when the act of comparing the read data from the write data shows disagreement.

### Claim 3 (depends on 2)

The method of claim 2 wherein the act of iterating comprises:
incrementing a count for each iteration;
comparing the count to a maximum number of iterations for each iteration; and
ceasing iterating when the count equals or exceeds the maximum number of iterations.

### Claim 4 (depends on 2)

The method of claim 2 wherein the act of reading the selected memory cell comprises:
applying a drain current to the MOSFET;
measuring a drain-source voltage across the MOSFET;
comparing the measured voltage to a threshold voltage;
providing an indication of a first logical state when the measured voltage exceeds the threshold; and
providing an indication of a second logical state when the measured voltage does not exceed the threshold.

### Claim 5 (depends on 2)

The method of claim 2 wherein the act of reading data from the selected memory cell comprises:
applying a drain-source voltage to the MOSFET;
measuring a drain current through the MOSFET;
comparing the measured current to a threshold current;
providing an indication of a first logical state when the measured current does not exceed the threshold; and
providing an indication of a second logical state when the measured current exceeds the threshold.

### Claim 6

A method of operating a selected memory cell comprising:
applying a positive voltage to a gate of a MOSFET comprising the selected memory cell to form a channel;
storing data represented by a predetermined number of electrons in an island formed from conductive material in an anodically-defined pore in semiconductor material forming the channel within the MOSFET, the island insulated from the channel, the predetermined number of electrons corresponding to one of a plurality of entries that may be stored in the MOSFET;
accessing the selected memory cell at a time after the act of storing data;
sampling an electrical parameter manifested by the selected memory cell in response to a stimulus; and
determining which of the plurality of entries is stored in the selected memory cell from the sample of the electrical parameter.

### Claim 7 (depends on 6)

The method of claim 6 wherein the act of storing data comprises:
applying a voltage pulse across a drain and a source coupled to the channel to write data to the MOSFET, a voltage and a duration of the voltage pulse corresponding to one of the plurality of entries that may be stored in the MOSFET:
reading data from the MOSFET;
comparing the read data to the data written to the MOSFET; and
iterating the acts of applying a voltage pulse, reading data and comparing the read and write data when the act of comparing the read data to the write data shows disagreement.

### Claim 8 (depends on 7)

The method of claim 7 wherein the act of iterating comprises:
incrementing a count for each iteration;
comparing the count to a maximum number of iterations for each iteration; and
ceasing iterating when the count equals or exceeds the maximum number of iterations.

### Claim 9 (depends on 7)

The method of claim 7 wherein the act of reading data comprises:
applying a drain-source voltage to the MOSFET;
measuring a drain current through the MOSFET;
comparing the measured current to a plurality of threshold currents to determine which of a plurality of entries is stored in the MOSFET; and
providing an indication of which entry is stored in the MOSFET.

### Claim 10 (depends on 7)

The method of claim 7 wherein the act of reading data comprises:
applying a drain current to the MOSFET;
measuring a drain-source voltage across the MOSFET;
comparing the measured voltage to plurality of threshold voltages to determine which of a plurality of entries is stored in the MOSFET; and
providing an indication of which entry is stored in the MOSFET.