# US 6,297,705 B1 · Circuit for locking an oscillator to a data stream > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,297,705 B1 - Document ID: US6297705B1 - Status: Granted - Kind: B1 - Application number: 09/511,020 - Filed: 2000-02-23 - Granted: 2001-10-02 - Earliest claimed: 2000-02-23 - Assignees: Cypress Semiconductor Corporation - Inventors: Timothy J. Williams; Jeffrey D. Wick - Web page: https://patentgrep.com/patent/US6297705B1 ## CPC - H03L 7/08: Details of the phase-locked loop - H03L 7/0991: {the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814)} - H03L 2207/50: All digital phase-locked loop - H04L 7/0083: {taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks} - H04L 7/0331: {with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence)} - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract An apparatus comprising a control circuit and a first circuit. The first circuit may be configured to generate a calibration signal in response to an adjustment signal and a first control signal. The control circuit may be configured to generate (i) the first control signal, (ii) a second control signal and (iii) the adjustment signal in response to a rate of an input signal. ## Claims ### Claim 1 The apparatus comprises: a first circuit comprising one or more counters, said first circuit configured to generate a calibration signal and an output signal in response to an adjustment signal and a first control signal; and a control circuit configured to generate (i) said first control signal, (ii) a second control signal and (iii) said adjustment signal in response to a rate of an input signal. ### Claim 2 (depends on 1) The circuit according to claim 1, further comprising: an oscillator circuit configured to generate a clock signal in response to said second control signal and said calibration signal. ### Claim 3 The apparatus comprises: a first circuit configured to generate a calibration signal in response to (i) a coarse/fine adjustment signal and (ii) a first control signal; and a control circuit configured to generate (i) said first control signal, (ii) a second control signal and (iii) said adjustment signal in response to a rate of an input signal. ### Claim 4 (depends on 3) The apparatus according to claim 3, wherein said first circuit comprises: one or more counters configured to generate an output in response to said adjustment signal and said first control signal. ### Claim 5 (depends on 1) The apparatus according to claim 1, wherein said first circuit further comprises a look-up table configured to generate said calibration signal. ### Claim 6 (depends on 1) The apparatus according to claim 1, wherein said oscillator circuit comprises: an oscillator control circuit configured to generate a multi-bit digital word; and an oscillator configured to generate said clock signal in response to said multi-bit digital word. ### Claim 7 (depends on 6) The apparatus according to claim 6, wherein said oscillator comprises a programmable oscillator. ### Claim 8 (depends on 5) The apparatus according to claim 5, wherein said multi-bit digital word is generated in response to said second control signal and said calibration signal. ### Claim 9 (depends on 8) The apparatus according to claim 8, wherein said oscillator control circuit comprises an oscillator setting block and an adder circuit. ### Claim 10 (depends on 1) The apparatus according to claim 1, wherein said adjustment signal comprises a coarse/fine adjustment signal. ### Claim 11 (depends on 4) The apparatus according to claim 4, wherein said first control signal is configured to start and stop said one or more counters. ### Claim 12 An apparatus comprising: an oscillator circuit configured to generate a clock signal in response to a first control signal and a calibration signal; and a first circuit configured to generate said calibration signal and said control signal in response to a rate of an input signal, wherein said first circuit comprises (a) a counter circuit configured to generate said calibration signal in response to an adjustment signal and a second control signal and (b) a control circuit configured to generate (i) said first control signal, (ii) said second control signal and (iii) said adjustment signal in response to a rate of an input signal. ### Claim 13 A method for locking a clock signal to a rate of a data stream comprising the steps of: (A) generating a multi-bit word; (B) generating said clock signal in response to a first control signal, a calibration signal and said multi-bit digital word; and (C) generating said calibration signal and said first control signal in response to a rate of an input signal. ### Claim 14 (depends on 13) The method according to claim 13, wherein step (C) further comprises the steps of: generating said calibration signal in response to an adjustment signal and a second control signal; and generating (i) said first control signal, (ii) said second control signal and (iii) said adjustment signal in response to a rate of an input signal. ### Claim 15 (depends on 13) The method according to claim 13, wherein said multi-bit digital word is generated in response to said first control signal and said calibration signal. ### Claim 16 (depends on 14) The method according to claim 14, wherein said adjustment signal comprises a coarse/fine adjustment signal. ### Claim 17 (depends on 14) The method according to claim 14, wherein step (B) is further configured to start and stop in response to said second control signal. ### Claim 18 (depends on 1) The apparatus according to claim 1, wherein said calibration signal is used to control an oscillator in a Universal Serial Bus device. ### Claim 19 (depends on 11) The apparatus according to claim 11, wherein said oscillator circuit is used in a Universal Serial Bus device.