Bias rail buffer circuit and method

A buffered current source having a bias rail buffer circuit for providing a stable reference signal, said buffered circuit source comprising:

• a buffer, said buffer comprising:
• an input transistor, a collector of which is coupled to an input reference;
• a first pair of complementary transistors, emitters of which are coupled to a base of said input transistor, and collectors of which are coupled to at least one voltage supply rail;
• and
• a second pair of complementary transistors, emitters of which are coupled together, and collectors of which are coupled to said at least one voltage supply rail, and a base of one of said second pair of transistors being coupled to a base of one of said first pair of complementary transistors;
• and
• a current source, said current source comprising an output transistor, a collector of which is coupled to an output reference, a base of which is coupled to said emitters of said second pair of complementary transistors, and an emitter of which is coupled through a resistor to said at least one voltage supply rail, and
• wherein external disturbances imparted onto said output reference appearing at said base of said output transistor are absorbed by said buffer by sourcing and sinking of current into said base of said output transistor.

A buffer for use in stabilizing an input reference signal, said buffer comprising:

• a first pair of complementary transistors comprising a first transistor and a second transistor, each of said first transistor and said second transistor having an emitter coupled to said input reference signal, said first transistor having a base coupled to said input reference signal, and said second transistor having a base and a collector connected together;
• and
• a second pair of complementary transistors comprising a third transistor and a fourth transistor, each of said third transistor and said fourth transistor having an emitter coupled to an output reference signal, said third transistor having a base connected to said input reference signal, and said fourth transistor having a base connected to said base of said second transistor;
• wherein said buffer is configured to source and sink current in said output reference signal to absorb external disturbances imparted on said output reference signal.

A bias rail buffer circuit for providing a stable reference signal, said bias rail buffer circuit comprising:

• an input transistor, a collector of which is coupled to an input reference signal;
• a first pair of complementary transistors, emitters of which are coupled to a base of said input transistor;
• and
• a second pair of complementary transistors, bases of which are coupled to bases of said first pair of complementary transistors, and emitters of which are coupled to an output reference signal;
• and
• wherein said second pair of complementary transistors source current to and sink current from said output reference signal to absorb external disturbances imparted on said output reference signal.