# US 6,297,686 B1 · Semiconductor integrated circuit for low-voltage high-speed operation

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- Number: US 6,297,686 B1
- Document ID: US6297686B1
- Status: Granted
- Kind: B1
- Application number: 09/321,849
- Filed: 1999-05-28
- Granted: 2001-10-02
- Earliest claimed: 1999-05-28
- Assignees: Winbond Electronics Corp.
- Inventors: Shi-Tron Lin; Yung-Chow Peng
- Web page: https://patentgrep.com/patent/US6297686B1

## CPC

- H03K 19/01707: {in asynchronous circuits}
- H03K 19/0016: {by using a control or a clock signal, e.g. in order to apply power supply}
- H10D 30/6706: {for preventing leakage current (TFTs characterised by the properties of the source or drain H10D30/6713)}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

For low-voltage and high-speed operation of a MOSFET in an integrated circuit, a small voltage is applied to a source node, causing slight forward bias of the source junction and thereby reducing its threshold voltage. Due to the combined effects of the bias at the source node and a body effect, the reduction in threshold voltage is larger than the absolute value of the source voltage being applied. A performance improvement over simply applying a bias voltage to the body (well) results. Detection of an event can be used to apply the performance boost to a critical path in the integrated circuit only when needed. Upon detection of a logic event, which determines that a signal will propagate through the critical path shortly thereafter, the source-node bias for circuit elements in the critical path can be adjusted in time for a speed improvement. However, the source remains at another potential when no signal is passing through the critical-path, to save power when not boosting speed.

## Claims

### Claim 1

An apparatus, comprising:
a first CMOS circuit having a first NMOSFET and a first PMOSFET;
a second CMOS circuit having a second NMOSFET and a second PMOSFET;
a first power node coupled to a source terminal of the first NMOSFET;
a second power node selectively coupled to a source terminal of the second NMOSFET; and
a third power node coupled to source terminals of the first and second PMOSFETs;
wherein the source terminal of the second NMOSFET is forward biased with respect to its substrate.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein substrate of the first and second NMOSFETs are coupled to the first power node.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein a voltage difference between the first and second power nodes is at most 0.65V.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the source terminal of the second NMOSFET is connected to the first power terminal when the second CMOS circuit is in stand-by mode.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the first and second CMOS circuits are in different integrated circuits.

### Claim 6

An integrated circuit comprising:
a first supply voltage node and a second supply voltage node;
a first gate connected by the first and second supply voltage nodes;
a second gate connected by the first and second supply voltage nodes and a bias voltage node such that the second gate functions faster than the first gate, the second gate being coupled to an output of the first gate; and
a level shifter connected between the first and second gates, to shift a level of the output of the first gate so that it can effectively operate the second gate.

### Claim 7 (depends on 6)

The integrated circuit of claim 6, wherein the level shifter includes a level shifting circuit connected to the bias voltage node.

### Claim 8 (depends on 6)

The integrated circuit of claim 6, wherein the level shifter includes a third gate connected to a modified bias voltage, which is derived from the bias voltage node.

### Claim 9 (depends on 6)

The integrated circuit of claim 6, wherein the level shifter includes a transistor having both its source and substrate connected he bias voltage node.

### Claim 10 (depends on 6)

The integrated circuit of claim 6, wherein the bias voltage node is coupled to a source node of an NMOSFET of the second gate.

### Claim 11 (depends on 10)

The integrated circuit of claim 10, wherein the bias voltage causes a forward bias of the source node to the substrate of the NMOSFET.