# US 6,297,672 B1 · CMOS integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,297,672 B1 - Document ID: US6297672B1 - Status: Granted - Kind: B1 - Application number: 09/171,430 - Filed: 1998-10-19 - Granted: 2001-10-02 - Earliest claimed: 1997-02-26 - Assignees: Advantest Corporation - Inventors: Toshiyuki Okayasu - Web page: https://patentgrep.com/patent/US6297672B1 ## CPC - H04L 25/0294: {Provision for current-mode coupling} - H03K 19/018521: {of complementary type, e.g. CMOS} - H03K 19/018571: {of complementary type, e.g. CMOS} - H04L 25/0282: {Provision for current-mode coupling} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract In a ultra-large scale integrated circuit of CMOS structure, high speed operation can be performed without being affected by the wiring capacitance and the gate input capacitance. A current-output type gate is used as a transmitting gate 11, and a capacitor 54 is charged or discharged only during the transition time of a signal. The charge or discharge current is multiplied by current Miller circuits 55, 56 to supply the current to a conductive path 15. A current-input type gate is used as a receiving gate 31. This gate 31 is arranged such that the output and input ends of an inverter 35 of CMOS structure are interconnected, respective ends of the inverter to be connected to power supplies are connected to a positive power supply terminal 16 through the current Miller circuit of p-channel MOS.FETs 37, 39 and connected to a negative power supply terminal 17 through the current Miller circuit of n-channel MOS.FETs 38, 41 respectively, and the output ends of both the current Miller circuits are connected to the signal transmission path 15. ## Claims ### Claim 1 An integrated circuit of CMOS structure comprising: a signal transmission path having an impedance in the integrated circuit; a current-input type gate having an input terminal coupled to said signal transmission path and receiving an input current via said input terminal, said current-input type gate having a low input impedance relative to said impedance of said signal transmission path and generating an output voltage depending upon the magnitude of the input current; a first current mirror circuit constituted by p-channel MOS.FETs, said first current mirror circuit connecting one of terminals which are to be connected to power supply terminals, of said current-input type gate to a positive power supply terminal; and a second current mirror circuit constituted by n-channel MOS.FETs, said second current mirror circuit connecting the other of terminals which are to be connected to power supply terminals, of said current-input type gate to a negative power supply terminal, and wherein said current-input type gate includes an inverter of CMOS structure the output end of which is connected to said input terminal, one of terminals of said inverter to be connected to power supply terminals is connected to said positive power supply terminal via said first current mirror circuit, the other of terminals of said inverter to be connected to power supply terminals is connected to said negative power supply terminal via said second current mirror circuit, and a mid point potential between the positive and negative power supply voltages is applied to the input end of said inverter. ### Claim 2 (depends on 1) The integrated circuit of CMOS structure according to claim 1, wherein an n-channel MOS.FET is inserted in series between said input terminal and the input side of said first current mirror circuit, a potential of addition of the mid point potential between said positive and negative power supply voltages and a threshold voltage of said n-channel MOS.FET is applied to gate of said n-channel MOS.FET, a p-channel MOS.FET is inserted in series between said input terminal and the input side of said second current mirror circuit, and a potential of subtraction of a threshold voltage of said p-channel MOS.FET from said mid point potential between said positive and negative power supply voltages is applied to gate of said p-channel MOS FET. ### Claim 3 (depends on 1, 2) The integrated circuit of CMOS structure according to claim 1 or 2, wherein a gate at the transmitting side in respect to said signal transmission path is a current-output type gate. ### Claim 4 (depends on 3) The integrated circuit of CMOS structure according to claim 3, wherein said current-output type gate is an inverter of CMOS structure. ### Claim 5 (depends on 3) The integrated circuit of CMOS structure according to claim 3, wherein said current-output type gate is a gate arranged such that the output end of an inverter of CMOS structure is grounded through a capacitor, respective ends of said inverter to be connected to power supplies are connected to a positive power supply terminal through a first current mirror circuit constituted by p-channel MOS.FETs and connected to a negative power supply terminal through a second current mirror circuit constituted by n-channel MOS.FETs respectively, and the output ends of said first and second current mirror circuits are connected to said signal transmission path. ### Claim 6 (depends on 5) The integrated circuit of CMOS structure according to claim 5, wherein a resistance element for maintaining a current is connected in parallel with said capacitor.