Multipurpose defect test structure with switchable voltage contrast capability and method of use

A test structure for detecting the presence of defects in conductive features formed on an integrated circuit topography comprising:

• a first conductive line formed upon the integrated circuit topography, the first conductive line comprising a main portion and projections extending from the main portion;
• a first transistor coupled to the main portion of the first conductive line, wherein the first transistor is configured to couple the first conductive line to ground, and wherein the first transistor is configured to disconnect the first conductive line from the ground when a first voltage is applied to the first transistor;
• a substantially ungrounded second conductive line formed upon the integrated circuit topography, wherein the second conductive line substantially surrounds the projections of the first conductive line such that a distance between the second conductive line and the first conductive line is substantially constant;
• a third conductive line formed upon the integrated circuit topography at a constant distance from the second conductive line;
• a second transistor coupled to the third conductive line, wherein the second transistor is configured to couple the third conductive line to the ground, and wherein the second transistor is configured to disconnect the third conductive line from the ground when a second voltage is applied to the second transistor;
• a pad coupled to the first and second transistors, wherein the pad is configured to receive an electrical testing probe, and wherein applying a voltage of sufficient magnitude to the pad causes the first and second transistors to disconnect the first and third conductive lines from the ground;
• and
• a fourth conductive line formed upon the integrated circuit topography at a constant distance from third conductive line, the fourth conductive line comprising a main portion and projections extending from the main portion.

A method for detecting defects in a conductive feature formed on an integrated circuit topography comprising:

• forming a test structure on the integrated circuit topography, the test structure comprising:
• a first conductive line formed upon the integrated circuit topography, wherein the first conductive line is selectively grounded by a transistor connected to the first conductive line and a voltage applied to the transistor;
• and
• a substantially ungrounded second conductive line formed upon the integrated circuit topography;
• irradiating the test structure with electrons;
• and
• inspecting the test structure while the test structure is irradiated with electrons.

A method for detecting defects in a conductive feature formed on an integrated circuit topography comprising:

• forming a test structure on the integrated circuit topography, the test structure comprising:
• a first conductive line formed upon the integrated circuit topography, the first conductive line comprising a main portion and projections extending from the main portion;
• a first transistor coupled to the main portion of the first conductive line, wherein the first transistor is configured to couple the first conductive line to ground, and wherein the first transistor is configured to disconnect the first conductive line from the ground when a first voltage is applied to the first transistor;
• a substantially ungrounded second conductive line formed upon the integrated circuit topography, wherein the second conductive line substantially surrounds the projections of the first conductive line such that a distance between the second conductive line and the first conductive line is substantially constant;
• a third conductive line formed upon the integrated circuit topography at a constant distance from the second conductive line;
• a second transistor coupled to the third conductive line, wherein the second transistor is configured to couple the third conductive line to ground, and wherein the second transistor is configured to disconnect the third conductive line from the ground when a second voltage is applied to the second transistor;
• a pad coupled to the first and second transistors, wherein the pad is configured to receive an electrical testing probe, and wherein applying a voltage to the pad causes the first and second transistors to disconnect the first and third conductive lines from the ground;
• and;
• a fourth conductive line formed upon the integrated circuit topography at a constant distance from third conductive line, the fourth conductive line comprising a main portion and projections extending from the main portion;
• irradiating the test structure with electrons;
• and
• inspecting the test structure while the test structure is irradiated with electrons.

A method for determining a defect size distribution of an extra material defect comprising:

• forming a test structure on an integrated circuit topography, the test structure comprising:
• a first conductive line formed upon the integrated circuit topography;
• a first transistor coupled to the first conductive line, wherein the first transistor couples the first conductive line to ground, and wherein the first transistor is configured to disconnect the first conductive line from the ground when a voltage is applied to the first transistor;
• a substantially ungrounded second conductive line formed upon the integrated circuit topography, wherein the second conductive line is positioned a first distance from the first conductive line;
• a third conductive line formed upon the integrated circuit topography at a second distance from the second conductive line;
• a second transistor coupled to the third conductive line, wherein the second transistor is configured to couple the third conductive line to ground, and wherein the second transistor is configured to disconnect the third conductive line from the ground when a voltage is applied to the second transistor;
• a fourth conductive line formed upon the integrated circuit topography at a third distance from third conductive line, the fourth conductive line comprising a main portion and projections extending from the main portion;
• irradiating the test structure with electrons;
• inspecting the test structure while the test structure is irradiated with electrons;
• electrically testing the conductive lines to determine the size of an extra material defect.