# US 6,297,563 B1 · Bonding pad structure of semiconductor device

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- Number: US 6,297,563 B1
- Document ID: US6297563B1
- Status: Granted
- Kind: B1
- Application number: 09/407,910
- Filed: 1999-09-29
- Granted: 2001-10-02
- Earliest claimed: 1998-10-01
- Assignees: Yamaha Corporation
- Inventors: Takahisa Yamaha
- Web page: https://patentgrep.com/patent/US6297563B1

## CPC

- H10W 72/019: {of bond pads}
- H10W 72/90: Bond pads, in general
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9232: {with additional elements interposed between layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/983: {Reinforcing structures, e.g. collars}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device having a semiconductor substrate and a bonding pad portion formed on the semiconductor substrate, the bonding pad portion having: an insulating film formed on the semiconductor substrate and a first-level conductive pad layer of a large island shape formed on the insulating film; first-level to (n−1)-level (n is an integer of 3 or larger) interlayer insulating films formed on and over the insulating film; second-level to n-level conductive pad layers formed on the interlayer insulating films in areas generally corresponding to an area where the first conductive pad layer was formed; a plurality of small diameter first through holes from the first-level to (n−1) level formed through the first-level to (n−1) level interlayer insulating films in areas generally corresponding to an area where the first conductive pad layer; a plurality of first contact plugs filled in the small diameter first through holes from the first-level to (n−1)-level, the first contact plugs at each level being conductive and electrically connecting two conductive pad layers adjacent along a normal to a surface of the semiconductor substrate, among the first-level to n-level conductive pad layers disposed in and on the first-level to (n−1)-level interlayer insulating films; an n-level interlayer insulating film formed on the (n−1)-level interlayer insulating film and covering the n-level conductive pad; a large diameter through hole formed through the n-level interlayer insulating film in an area corresponding to an area where the n-level conductive pad was formed, the large diameter through hole having a size corresponding to the n-level conductive pad to expose a substantial upper surface of the n-level conductive pad; and a bonding pad formed on the n-level interlayer insulating film and n-level conductive pad via the large diameter through hole.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate; and
a bonding pad portion formed on said semiconductor substrate, said bonding pad portion comprising:
an insulating film formed on said semiconductor substrate and a first-level conductive pad layer of a large island shape formed on said insulating film;
first-level to (n−1)-level (n is an integer of 3 or larger) interlayer insulating films formed on and over said insulating film;
second-level to n-level conductive pad layers formed on said interlayer insulating films in areas generally corresponding to an area where said first conductive pad layer was formed;
a plurality of small diameter first through holes from the first-level to (n−1) level formed through said first-level to (n−1) level interlayer insulating films in areas generally corresponding to an area where said first conductive pad layer is located;
a plurality of first contact plugs filled in said small diameter first through holes from the first-level to (n−1)-level, said first contact plugs at each level being conductive and electrically connecting two conductive pad layers adjacent along a normal to a surface of said semiconductor substrate, among said first-level to n-level conductive pad layers disposed in and on said first-level to (n−1)-level interlayer insulating films;
an n-level interlayer insulating film formed on said (n−1)-level interlayer insulating film and covering said n-level conductive pad;
a large diameter through hole formed through said n-level interlayer insulating film in an area corresponding to an area where said n-level conductive pad was formed, said large diameter through hole having a size corresponding to said n-level conductive pad to expose a substantial upper surface of said n-level conductive pad; and
a bonding pad formed on said n-level interlayer insulating film and n-level conductive pad via said large diameter through hole.

### Claim 2 (depends on 1)

A semiconductor device according to claim 1, further comprising a wiring portion comprising:
first-level to n-level wiring layers formed on and over said semiconductor substrate at same levels as said first-level to n-level conductive pad layers;
a highest-level wiring layer formed on said n-level interlayer insulating film;
small diameter second through holes formed through said first-level to n-level interlayer insulating films; and
a plurality of second contact plugs filled in said small diameter second through hole from the first-level to n-level, said second contact plug at each level being conductive and electrically connecting two wring layers adjacent along a normal to the surface of said semiconductor substrate, among said first-level to n-level wiring layers disposed in and on said first-level to n-level interlayer insulating films.

### Claim 3 (depends on 2)

A semiconductor device according to claim 2, further comprising wiring patterns for connecting said bonding pad layer and said wiring layer at a same-level.

### Claim 4 (depends on 3)

A semiconductor device according to claim 3, wherein said interlayer insulating film includes a coated insulating film.

### Claim 5 (depends on 4)

A semiconductor device according to claim 4, wherein said bonding pad portion is formed around said wiring portion.

### Claim 6 (depends on 4)

A semiconductor device according to claim 4, wherein said conductive pad layer includes a Ti layer, an Al—Cu alloy layer and a TiN layer.

### Claim 7 (depends on 4)

A semiconductor device according to claim 4, wherein said conductive pad layer includes an Al—Cu alloy layer and a TiN layer.

### Claim 8 (depends on 4)

A semiconductor device according to claim 4, wherein a diameter of said small diameter first through hole is two times or smaller than a diameter of said small diameter second through hole.

### Claim 9 (depends on 4)

A semiconductor device according to claim 4, wherein said first and second contact plugs are made of W.

### Claim 10 (depends on 4)

A semiconductor device according to claim 4, wherein said first and second contact plugs each comprise:
a first layer of Ti, Ti/TiN or TiN covering an inner surface of each of said small diameter first and second through holes; and W layer formed thereon.

### Claim 11 (depends on 4)

A semiconductor device according to claim 4, wherein said interlayer insulating film contains silicon oxide.

### Claim 12 (depends on 4)

A semiconductor device according to claim 4, wherein a silicon oxide film and a silicon nitride film are formed on said n-level interlayer insulating film.