# US 6,297,561 B1 · Semiconductor chip

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- Number: US 6,297,561 B1
- Document ID: US6297561B1
- Status: Granted
- Kind: B1
- Application number: 09/630,529
- Filed: 2000-08-01
- Granted: 2001-10-02
- Earliest claimed: 1999-05-26
- Assignees: United Microelectronics Corp.
- Inventors: Hermen Liu; Yimin Huang
- Web page: https://patentgrep.com/patent/US6297561B1

## CPC

- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/075: {of bond wires}
- H10W 72/07553: {changes in shapes}
- H10W 72/251: {Materials}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/531: {Shapes of wire connectors}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/552: {comprising metals or metalloids, e.g. silver}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/90: Bond pads, in general
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/951: {Materials of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/983: {Reinforcing structures, e.g. collars}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention provides a semiconductor chip. The semiconductor chip comprising an integrated circuit (IC) positioned within the semiconductor chip, and a bonding pad positioned on the surface of the semiconductor chip and electrically connected with the IC. The method comprises using a probe to contact a predetermined testing area on the surface of the bonding pad to electrically test the IC, and forming a passivation layer on the surface of the semiconductor chip to passivate the surface of the semiconductor chip. The testing area of the bonding pad is covered under the passivation layer and the passivation layer comprises an opening positioned on the bonding pad outside the testing area which is used as a connecting area for performing wire bonding or bumping.

## Claims

### Claim 1

A semiconductor chip comprising:
an integrated circuit (IC) in the semiconductor chip;
a bonding pad positioned on a surface of the semiconductor chip and electrically connected to the integrated circuit, the bonding pad comprising a testing area that is a portion of its surface for performing an electrical test of the integrated circuit, and a connecting area, not overlapped with the testing area, for performing wire bonding or bumping directly on the surface of the bonding pad; and
a passivation layer covered on the surface of the semiconductor chip for passivating the surface of the semiconductor chip;
wherein the passivation layer comprises an opening positioned on the connecting area of the bonding pad, and the testing area of the bonding pad is covered by the passivation layer.

### Claim 2 (depends on 1)

The semiconductor chip of claim 1 wherein the electrical test of the integrated circuit is performed by using a probe to contact the testing area on the surface of the bonding pad.

### Claim 3 (depends on 1)

The semiconductor chip of claim 1 wherein the bonding pad is a metallic layer formed of aluminum (Al), copper (Cu) or alloy of aluminum.

### Claim 4 (depends on 3)

The semiconductor chip of claim 3 wherein the alloy is formed of aluminum and copper with more than 95% of aluminum by weight.

### Claim 5 (depends on 1)

The semiconductor chip of claim 1 wherein the bonding pad comprises a glue layer formed of titanium (Ti) positioned on the surface of the semiconductor chip, an aluminum alloy layer positioned on the glue layer, and an anti-reflection layer formed of titanium nitride (TiN) positioned on the surface of the aluminum alloy layer.

### Claim 6 (depends on 1)

The semiconductor chip of claim 1 wherein the passivation layer comprises an inorganic passivation layer positioned on the surface of the semiconductor chip and an organic passivation layer positioned on the inorganic passivation layer.

### Claim 7 (depends on 6)

The semiconductor chip of claim 6 wherein the inorganic passivation layer is formed of phosphosilicate glass (PSG) or silicon nitride.

### Claim 8 (depends on 6)

The semiconductor chip of claim 6 wherein the organic passivation layer is formed of polyimide.

### Claim 9 (depends on 1)

The semiconductor chip of claim 1 wherein the opening is formed by performing photolithographic and dry etching processes.

### Claim 10 (depends on 9)

The semiconductor chip of claim 9 wherein the dry etching process is performed by injecting a mixed gas at a low pressure over which the mixed gas comprises sulfur hexafluoride (SF6), fluoroform (CHF3), and carbon tetrafluoride (CF4).