# US 6,297,524 B1 · Multilayer capacitor structure having an array of concentric ring-shaped plates for deep sub-micron CMOS

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- Number: US 6,297,524 B1
- Document ID: US6297524B1
- Status: Granted
- Kind: B1
- Application number: 09/542,712
- Filed: 2000-04-04
- Granted: 2001-10-02
- Earliest claimed: 2000-04-04
- Assignees: Philips Electronics North America Corporation
- Inventors: Vickram Vathulya; Tirdad Sowlati
- Web page: https://patentgrep.com/patent/US6297524B1

## CPC

- H10D 1/711: {having non-planar surfaces, e.g. formed by texturisation}
- H10D 84/212: {of only capacitors}
- H10W 20/496: {Capacitor integral with wiring layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A capacitor structure having a first and at least a second conductor level of electrically conductive concentric ring-shaped lines. The conductive lines of the first and at least second levels are arranged in concentric ring-shaped stacks. A dielectric material is disposed between the first and second conductor levels and between the concentric conductive lines in each of the levels. At least one electrically conductive via electrically connects the conductive lines in each stack, thereby forming a concentric array of ring-shaped capacitor plates. The concentric array of capacitor plates are electrically connected in an alternating manner to first and second terminals of opposite polarity so that capacitance is generated between adjacent plates of the array. The capacitor structure is especially useful in deep sub-micron CMOS.

## Claims

### Claim 1

A capacitor comprising:
a first conductor level of electrically conductive concentric lines;
at least a second conductor level of electrically conductive concentric lines, the conductive lines of the first and at least second levels arranged in concentric stacks;
a dielectric material disposed between the first and second conductor levels and between the concentric conductive lines in each of the levels;
at least one electrically conductive via electrically connecting the conductive lines in each stack, thereby forming an array of concentric capacitor plates, each conductive via extending through the dielectric material between the first and second conductor levels; and
first and second terminals having opposite electrical polarities;
wherein the array of concentric capacitor plates are electrically connected in an alternating manner to the terminals of opposite polarity so that capacitance is generated between adjacent plates of the array.

### Claim 2 (depends on 1)

The capacitor according to claim 1, wherein the conductive lines and the plates formed thereby have a ring-shaped structure.

### Claim 3 (depends on 1)

The capacitor according to claim 1, wherein the conductive lines and the plates formed thereby have a square ring-shaped structure.

### Claim 4 (depends on 1)

The capacitor according to claim 1, wherein the capacitor is constructed over a substrate.

### Claim 5 (depends on 4)

The capacitor according to claim 4, wherein the substrate is made from a semiconductor material.

### Claim 6 (depends on 1)

The capacitor according to claim 1, wherein the capacitor comprises a sub-micron MOS structure.

### Claim 7 (depends on 1)

The capacitor according to claim 1, wherein the capacitor comprises a sub-micron CMOS structure.

### Claim 8 (depends on 1)

The capacitor of claim 1, wherein the capacitor comprises a sub-micron structure.

### Claim 9 (depends on 1)

The capacitor according to claim 1, wherein the conductive lines are made from one of a metal material and a conductive semiconductor material.

### Claim 10 (depends on 1)

The capacitor according to claim 1, wherein the at least second conductor level of electrically conductive concentric lines is a plurality of conductor levels of electrically conductive concentric lines, the conductive lines of all the levels arranged in concentric stacks.

### Claim 11 (depends on 1)

The capacitor according to claim 1, wherein the at least one electrically conductive via is a plurality of electrically conductive vias.