# US 6,297,155 B1 · Method for forming a copper layer over a semiconductor wafer

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- Number: US 6,297,155 B1
- Document ID: US6297155B1
- Status: Granted
- Kind: B1
- Application number: 09/305,093
- Filed: 1999-05-03
- Granted: 2001-10-02
- Earliest claimed: 1999-05-03
- Assignees: Motorola, Inc.
- Inventors: Cindy Reidsema Simpson; Robert Douglas Mikkola; Matthew T. Herrick; Brett Caroline Baker; David Moralez Pena; Edward Acosta; Rina Chowdhury; Marijean Azrak; Cindy Kay Goldberg; Mohammed Rabiul Islam
- Web page: https://patentgrep.com/patent/US6297155B1

## CPC

- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10P 14/47: Electrolytic deposition, i.e. electroplating; Electroless plating
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for electroplating a copper layer (118) over a wafer (20) powers a cathode of an electroplating system (10) in a manner that obtains improved copper interconnects. A control system (34) powers the cathode of the system (10) with a mix of two or more of: (i) positive low-powered DC cycles (201 or 254); (ii) positive high-powered DC cycles (256 or 310); (iii) low-powered, pulsed, positive-power cycles (306 or 530); (iv) high-powered, pulsed, positive-powered cycles (212, 252, 302, or 352); and/or (v) negative pulsed cycles (214, 304, 510, 528, or 532). The collection of these cycles functions to electroplate copper or a like metal (118) onto the wafer (20). During electroplating, insitu process control and/or endpointing (506, 512, or 520) is performed to further improve the resulting copper interconnect.

## Claims

### Claim 1

A method for forming a copper layer over a wafer, the method comprising the steps of:
placing the wafer in an electroplating chamber, the electroplating chamber having a control system wherein the control system is electrically coupled to the wafer through at least one electrical contact that provides power to the wafer;
providing a first power to the wafer at a first power level for a first time period; and
positively pulsing a second power to the wafer during a second time period following the first time period, the second power having on time periods and off time periods, and wherein: (1) a second power level that is supplied to the wafer during the on time periods of the second time period is greater than the first power level used during the first time period; and (2) a third power level that is supplied to the wafer during the off time periods of the second time period is less than the first power level used during the first time period.

### Claim 2 (depends on 1)

The method of claim 1, further comprising negatively pulsing a third power to the wafer during a third time period following the second time period.

### Claim 3 (depends on 2)

The method of claim 2, further comprising positively pulsing a fourth power to the wafer during a fourth time period following the third time period.

### Claim 4 (depends on 3)

The method of claim 3, further comprising providing a positive power having a DC constant level to the wafer during a fifth time period following the fourth time period.

### Claim 5 (depends on 4)

The method of claim 4, wherein a magnitude of the positive power having a DC constant level is greater than a magnitude of the second power level used during the second time period.

### Claim 6 (depends on 1)

The method of claim 1, wherein the copper layer is formed overlying a seed layer that has been formed using chemical vapor deposition (CVD).

### Claim 7 (depends on 1)

The method of claim 1, wherein the copper layer forms portions of a dual inlaid interconnect structure.

### Claim 8 (depends on 1)

The method of claim 1, wherein an insitu endpoint detection step is performed sometime during formation of the copper layer over the wafer.

### Claim 9

A method for forming a copper layer over a wafer, the method comprising the steps of:
placing the wafer in an electroplating chamber, the electroplating chamber having a control system, wherein the control system is electrically coupled to the wafer through at least one electrical contact, and wherein the control system provides power to the wafer;
positively pulsing power to the wafer during a first time period, wherein positively pulsing power has on periods at a first power level and off periods at a second power level;
providing a first constant power to the wafer during a second time period following the first time period, wherein the first constant power has a third power level that is less than the first power level and greater than the second power level; and
providing a second constant power to the wafer during a third time period following the second time period, wherein the second constant power has a fourth power level that is greater than the first power level.

### Claim 10 (depends on 9)

The method of claim 9, wherein the copper layer is used to form a dual inlaid interconnect structure.

### Claim 11 (depends on 9)

The method of claim 9, wherein an insitu endpoint detection step is performed sometime during formation of the copper layer over the wafer.

### Claim 12

A method for forming a copper layer over a wafer, the method comprising the steps of:
placing the wafer in an electroplating chamber, the electroplating chamber having a control system, wherein the control system is electrically coupled to the wafer through at least one electrical contact, and wherein the control system provides power to the wafer; and
pulsing power to the wafer, wherein the pulsing power comprises a first on time period and a second on time period, wherein a first power level applied during the first on time period is associated with a first positive current and a second power level applied during the second on time period is associated with a second positive current, and wherein the first positive current is greater than the second positive current.

### Claim 13 (depends on 12)

The method of claim 12, wherein the second on time period is greater than the first on time period.

### Claim 14 (depends on 12)

The method of claim 12, wherein a level of impurities incorporated into the copper layer is greater during the second on time period than during the first on time period.

### Claim 15 (depends on 14)

The method of claim 14, wherein the impurities consist of an element selected from a group consisting of: sulfur, carbon and nitrogen.

### Claim 16 (depends on 12)

The method of claim 12, wherein an insitu endpoint detection step is performed sometime during formation of the copper layer over the wafer.

### Claim 17

A method for forming a copper layer over a wafer, the method comprising the steps of:
placing the wafer in an electroplating chamber, the electroplating chamber having a control system, wherein the control system is electrically coupled to the wafer through at least one electrical contact, and wherein the control system provides power to the wafer;
positively pulsing a first power to the wafer during a first time period, wherein positively pulsing the first power further comprises on time periods at a first power level and off periods at a second power level;
negatively pulsing a second power to the wafer during a second time period that follows the first time period, wherein negatively pulsing a second power further comprises on time periods at a third power level and off time periods at a fourth power level; and
positively pulsing a third power to the wafer during a third time period that follows the second time period, wherein positively pulsing the third power further comprises on time periods at a fifth power level and off time periods at a sixth power level wherein the fifth power level is less than the first power level.

### Claim 18 (depends on 17)

The method of claim 17, further comprising providing a constant positive power to the wafer during a fourth time period following the third time period.

### Claim 19 (depends on 17)

The method of claim 17, wherein the on time periods at a first power level are greater than the off time periods at a second power level, and wherein the on time periods at a fifth power level are greater than the off time periods at a sixth power level.

### Claim 20 (depends on 17)

The method of claim 17, wherein an insitu endpoint detection step is performed sometime during formation of the copper layer over the wafer.

### Claim 21

A method for forming a copper layer over a wafer, the method comprising the steps of:
placing the wafer in an electroplating chamber, the electroplating chamber having a control system, wherein the control system is electrically coupled to the wafer through at least one electrical contact, and wherein the control system provides power to the wafer; and
positively pulsing power to the wafer, wherein positively pulsing power comprises on time periods and off time periods, and wherein the on time periods are less than the off time periods.

### Claim 22 (depends on 21)

The method of claim 21, wherein the copper layer fills portions of a dual inlaid structure having dimensions smaller than 0.1 microns.

### Claim 23 (depends on 21)

The method of claim 21, wherein the copper layer fills portions of an opening having an aspect ratio of depth:width of greater than or equal to 6:1.

### Claim 24 (depends on 21)

The method of claim 21, wherein an insitu endpoint detection step is performed sometime during formation of the copper layer over the wafer.

### Claim 25

A method for forming a copper layer over a wafer, the method comprising the steps of:
placing the wafer in an electroplating chamber, wherein:
the wafer has a dual inlaid interconnect opening with a top dielectric surface, a bottom trench surface positioned at a planar surface below the top dielectric surface, and a bottom via surface positioned at a planar surface below the bottom trench surface, and
the electroplating chamber has a control system that is electrically coupled to the wafer through at least one electrical contact, and wherein the control system provides power to the wafer;
positively pulsing power to the wafer for a first time period;
negatively pulsing power to the wafer for a second time period following the first time period; and
positively pulsing power to the wafer for a third time period following the second time period.

### Claim 26 (depends on 25)

The method of claim 25, wherein a via opening of the dual inlaid interconnect opening is less than approximately 0.1 microns.

### Claim 27 (depends on 25)

The method of claim 25, wherein the dual inlaid interconnect opening further comprises a seed layer formed by physical vapor deposition (PVD).

### Claim 28 (depends on 27)

The method of claim 27, wherein portions of the seed layer formed on sidewall portions of the dual inlaid interconnect opening adjacent the top dielectric surface and the bottom trench surface are thicker than portions of the seed layer formed on sidewalls in regions closer to the bottom via surface.

### Claim 29 (depends on 27)

The method of claim 27, wherein sidewall portions of the dual inlaid interconnect opening between the bottom trench surface and the bottom via surface contain depletion regions which do not contain contiguous seed material.

### Claim 30 (depends on 25)

The method of claim 25, wherein an insitu endpoint detection step is performed sometime during formation of the copper layer over the wafer.

### Claim 31

A method for forming a copper layer over a wafer, the method comprising the steps of:
placing the wafer in an electroplating chamber, wherein the electroplating chamber has a control system that is electrically coupled to the wafer through at least one electrical contact, and wherein the control system provides power to the wafer;
powering the wafer to electroplate copper onto the wafer; and
monitoring an electrical property of the wafer during electroplating to determine when to change conditions in the electroplating chamber.

### Claim 32 (depends on 31)

The method of claim 31, wherein monitoring an electrical property is further characterized as providing current through the at least one electrical contact and measuring a voltage drop across the wafer.

### Claim 33 (depends on 31)

The method of claim 31, wherein monitoring an electrical property is further characterized as providing a voltage potential to the at least one electrical contact and measuring a corresponding current through the wafer.

### Claim 34 (depends on 31)

The method of claim 31, wherein powering the wafer and monitoring an electrical property are alternately performed during formation the copper layer through the same clamp mechanism in a time multiplexed manner.

### Claim 35 (depends on 31)

The method of claim 31, wherein powering the wafer is performed using a first set of electrical wafer contacts and monitoring an electrical property of the wafer is performed using a second set of electrical wafer contacts, wherein the first set of electrical contacts is different from the second set of electrical contacts.

### Claim 36 (depends on 31)

The method of claim 31, wherein powering the wafer is performed using a first set of electrical contacts and monitoring an electrical property is performed using a second set of electrical contacts of the wafer, wherein the first set of electrical contacts includes the second set of electrical contacts.

### Claim 37 (depends on 31)

The method of claim 31, wherein monitoring an electrical property and powering the wafer further comprises:
monitoring the electrical property at multiple points across the wafer to determine a uniformity of copper electroplated onto the wafer.

### Claim 38 (depends on 37)

The method of claim 37, wherein monitoring an electrical property and powering the wafer further comprises:
powering specific electrical contacts in response to the monitoring the electrical property at multiple points to insitu change the uniformity of copper electroplated onto the wafer.

### Claim 39 (depends on 31)

The method of claim 31, wherein powering the wafer is performed using a first set of electrical contacts in a first processing environment and monitoring an electrical property of the wafer is performed using a second set of electrical contacts in a second processing environment, and wherein the wafer is moved between the first processing environment and the second processing environment via robotic control.

### Claim 40

A method for forming a copper layer over a wafer, the method comprising the steps of:
placing the wafer in an electroplating chamber, the electroplating chamber having an control system, wherein the control system is electrically coupled to the wafer and to an anode, and wherein the control system provides power to the wafer and the anode;
positively powering the wafer to electroplate copper onto the wafer; and
pulsing power to the anode to further control an electroplating of copper onto the wafer.

### Claim 41 (depends on 40)

The method of claim 40, wherein an insitu endpoint detection step is performed sometime during formation of the copper layer over the wafer.

### Claim 42

A method for forming a copper layer over a wafer, the method comprising the steps of:
using one or more low-power positive pulsed or alternating current (AC) cycles in a plating chamber to fill a via opening with copper, the via opening having a radius less than 1.0 micron and being filled in a void-free manner; and
using a high-powered direct current (DC) cycle in the plating chamber to complete the copper layer over the wafer whereby wafer throughput through the plating chamber is improved.