# US 6,297,093 B1 · Method of making an electrically programmable memory cell

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- Number: US 6,297,093 B1
- Document ID: US6297093B1
- Status: Granted
- Kind: B1
- Application number: 09/276,003
- Filed: 1999-03-25
- Granted: 2001-10-02
- Earliest claimed: 1998-03-26
- Assignees: STMicroelectronics S.r.l.
- Inventors: Joseph Borel; Jean-Pierre Schoellkopf; Constantin Papadas
- Web page: https://patentgrep.com/patent/US6297093B1

## CPC

- H10D 30/0411: {of FETs having floating gates}
- H10D 30/6893: {wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present invention relates to a method of manufacturing an electrically programmable memory cell with a lateral floating gate with respect to the control gate, including the steps of forming an insulated control gate on an active area; forming a thin insulating layer around the control gate; successively depositing a thin layer of a conductive material and a layer of an insulating material; anisotropically etching the insulating material to form spacers of this material; and removing the portions of the thin conductive layer which are not coated with the spacers.

## Claims

### Claim 1

A method of manufacturing an electrically programmable memory cell, including steps of:
forming an insulated control gate on an active area of a semiconductor substrate;
forming a thin insulating layer around the control gate;
successively depositing a thin layer of a conductive material and a layer of an insulating material on the thin insulating layer;
anisotropically etching the insulating material to form insulating spacers of the insulating material; and
removing portions of the thin layer of the conductive material which are not coated with the insulating spacers to form a floating gate that is laterally arranged with respect to the control gate.

### Claim 2 (depends on 1)

The method of claim 1, wherein the conductive material is doped polysilicon.

### Claim 3

The method of claim l, wherein the conductive material has a thickness from 5 to 20 nm.

### Claim 4 (depends on 1)

The method of claim 1, wherein the insulating material is silicon nitride.

### Claim 5 (depends on 1)

The method of claim 1, further including a step of oxidizing apparent portions of the conductive material.

### Claim 6

A method of manufacturing an electrically programmable memory cell, including steps of:
forming an insulated control gate on an active area of a semiconductor substrate;
forming a thin insulating layer around the control gate;
successively depositing a thin layer of a conductive material and a layer of an insulating material on the thin insulating layer;
anisotropically etching the insulating material to form insulating spacers of the insulating material; and
removing portions of the thin layer of the conductive material which are not coated with the insulating spacers to form a floating gate that is laterally arranged with respect to the control gate and disposed between the control gate and the insulating spacers.

### Claim 7 (depends on 1)

The method of claim 1, wherein the active area of the semiconductor substrate is delimited by a thick oxide layer.

### Claim 8 (depends on 1)

The method of claim 1, wherein the conductive material is a metal.

### Claim 9 (depends on 8)

The method of claim 8, wherein the metal is aluminum.

### Claim 10 (depends on 1)

The method of claim 1, wherein the step of removing includes a step of exposing the thin insulating layer around the control gate.