# US 6,295,628 B1 · Logic synthesis method and device using similar circuit extraction

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- Number: US 6,295,628 B1
- Document ID: US6295628B1
- Status: Granted
- Kind: B1
- Application number: 08/885,898
- Filed: 1997-06-30
- Granted: 2001-09-25
- Earliest claimed: 1996-06-28
- Assignees: NEC Corporation
- Inventors: Atsushi Nakamura
- Web page: https://patentgrep.com/patent/US6295628B1

## CPC

- G06F 30/30: Circuit design
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A logic synthesizer includes a circuit analyzer for reading hardware function operation descriptions in hardware description language to translate the same into internal circuit expressions, a memory for storing circuits, common part information and restriction information, a hierarchically low level separator for separating hierarchically low level information that is commonly referenced, an output device for outputting a synthesis result, an optimization device for optimization processing, and a restriction condition input device for inputting restriction conditions. The circuit analyzer includes a basic analyzing device for basic analysis of the hardware descriptions, a similar description extraction element for extracting common and similar descriptions, and a hierarchically low level common device for translating the extracted common descriptions into common reference form at a hierarchically low level.

## Claims

### Claim 1

A method of optimization of logic synthesis comprising the steps of:
inputting hardware function operation descriptions for different parts of a single circuit in hardware descriptions language;
extracting common logics from the inputted hardware function operation descriptions for the different parts of the single circuit to translate the common logics into a common reference form at a hierarchically low level;
executing a first logical optimization for the common logics extracted from the different parts of the single circuit;
separating the first optimized common logics; and
executing a second logical optimization for each of the separated common logics based on each of boundary conditions of the separated common logics.

### Claim 2

A method of optimization of logic synthesis comprising the steps of:
inputting gate level net lists for different parts of a single circuit;
extracting common logics from the inputted gate level net lists for the different parts of the single circuit to translate the common logics into a common reference form at a hierarchically low level;
executing a first logical optimization for the common logics extracted from the different parts of the single circuit;
separating the first optimized common logics; and
executing a second logical optimization for each of the separated common logics based on each of boundary conditions of the separated common logics.