# US 6,295,620 B1 · Memory test facilitation circuit using stored test data repeatedly

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- Number: US 6,295,620 B1
- Document ID: US6295620B1
- Status: Granted
- Kind: B1
- Application number: 09/291,063
- Filed: 1999-04-14
- Granted: 2001-09-25
- Earliest claimed: 1998-04-22
- Assignees: Oki Electric Industry Co., Ltd.
- Inventors: Kiyotake Togo
- Web page: https://patentgrep.com/patent/US6295620B1

## CPC

- G11C 29/36: Data generation devices, e.g. data inverters
- G11C 29/10: Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
- G11C 29/14: Implementation of control logic, e.g. test mode decoders
- G11C 29/56: External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory device has a main memory circuit, an auxiliary memory circuit for storing test data, and an interface circuit for transferring test data between the auxiliary memory circuit and external test equipment. Test data are transferred from the external test equipment to the auxiliary memory circuit, then transferred repeatedly to different locations in the main memory circuit. Different test patterns are generated by selectively inverting one bit, or all bits, in the test data as the data are transferred into the main memory circuit. Test results are obtained by using a comparator in the memory device to compare the data stored in the auxiliary memory circuit with data read from the main memory circuit.

## Claims

### Claim 1

A test facilitation circuit integrated into a memory device having a main memory circuit with a plurality of memory cells, to facilitate testing of said main memory circuit by external test equipment, comprising:
a first auxiliary memory circuit storing test data;
an internal data bus coupling said first auxiliary memory circuit to said main memory circuit;
an interface circuit receiving address information, a read request signal, and a write request signal from said external test equipment, and transferring said test data to and from said external test equipment;
an auxiliary memory controller coupled to said interface circuit, controlling access to said first auxiliary memory circuit; and
a main memory controller coupled to said interface circuit, receiving a first test mode signal from said external test equipment, responding to said write request signal when said first test mode signal is in one state by directing said auxiliary memory controller to transfer said test data from said interface circuit to said first auxiliary memory circuit, then by transferring said test data from said first auxiliary memory circuit to said main memory circuit, and responding to said write request signal when said first test mode signal is another state by transferring test data previously stored in said first auxiliary memory circuit immediately from said first auxiliary memory circuit to said main memory circuit.

### Claim 2 (depends on 1)

The test facilitation circuit of claim 1, wherein said auxiliary memory controller sends said main memory controller a status signal, indicating storage of said test date in said first auxiliary memory circuit, upon completion of transfer of said test data from interface circuit to said first auxiliary memory circuit, and when said first test mode signal is in said one state, said main memory controller transfers said test data from said first auxiliary memory circuit to said main memory circuit in response to said status signal.

### Claim 3 (depends on 2)

The test facilitation circuit of claim 2, wherein said main memory controller comprises:
a first logic gate receiving said write request signal and said status signal;
a second logic gate receiving said write request signal and said first test mode signal;
an inverter receiving said first test mode signal;
a third logic gate receiving said write request signal and the inverted first test mode signal, thereby generating a signal controlling said auxiliary memory controller;
a fourth logic gate receiving inputs from said first logic gate and said second logic gate; and
a control signal generator generating control signals for said main memory circuit according to an output of said fourth logic gate.

### Claim 4 (depends on 1)

The test facilitation circuit of claim 1, further comprising:
a complementing circuit coupled to said first auxiliary memory circuit, generating a logical complement of the test data stored in said first auxiliary memory circuit; and
a multiplexer inserted in said internal data bus, receiving a second test mode signal from said external test equipment, selecting one of the test data stored in said first auxiliary memory circuit and the logical complement of said test data generated by said complementing circuit for transfer to said main memory circuit, responsive to said second test mode signal.

### Claim 5 (depends on 1)

The test facilitation circuit of claim 1, further comprising:
a complementing circuit coupled to said first auxiliary memory circuit, generating a logical complement of the test data stored in said first auxiliary memory circuit;
a counter receiving a second test mode signal from said external test equipment, generating a count signal by counting pulses of said second test mode signal; and
a multiplexer inserted in said internal data bus, selecting a bit of the test data output by said first auxiliary memory circuit according to said count signal, and replacing the selected bit with a complementary bit generated by said complementing circuit, for transfer to said main memory circuit.

### Claim 6 (depends on 1)

The test facilitation circuit of claim 1, further comprising:
a comparator coupled to said first auxiliary memory circuit, comparing the test data stored in said first auxiliary memory circuit with data read from said main memory circuit, and supplying a comparison result signal to said external test equipment.

### Claim 7 (depends on 6)

The test facilitation circuit of claim 6, further comprising:
a second auxiliary memory circuit coupled to said internal data bus, storing said data read from said main memory circuit; and
a logic circuit coupled to said auxiliary memory controller, receiving said first test mode signal, selecting one of said first auxiliary memory circuit and said second auxiliary memory circuit according to said first test mode signal, and causing said auxiliary memory controller to respond to said read request signal by transferring data from said main memory circuit to the selected auxiliary memory circuit.

### Claim 8 (depends on 1)

The test facilitation circuit of claim 1, further comprising:
an address counter coupled to said main memory controller, counting transfers of test data from said first auxiliary memory circuit to said main memory circuit, thereby generating internal address information; and
a multiplexer coupled to said address counter, selecting one of the address information received by said interface circuit and the internal address information generated by said address counter, for supply to said main memory circuit.

### Claim 9 (depends on 1)

The test facilitation circuit of claim 1, wherein said memory device is a dynamic random-access memory device.

### Claim 10

A method of testing a memory device having a main memory circuit and an auxiliary memory circuit, comprising the steps of:
transferring test data from external test equipment to said auxiliary memory circuit;
storing said test data in said auxiliary memory circuit;
generating a status signal indicating that said test data have been stored in said auxiliary memory circuit;
transferring said test data from said auxiliary memory circuit to one location in said main memory circuit, responsive to said status signal;
receiving a write request signal from said external test equipment; and
transferring said test data from said auxiliary memory circuit to another location in said main memory circuit, responsive to said write request signal.

### Claim 11 (depends on 10)

The method of claim 10, wherein said main memory circuit comprises a row-column array of memory cells, and said one location and said another location are disposed in different rows in said row-column array.

### Claim 12 (depends on 10)

The method of claim 10, further comprising the steps of:
sending a mode signal from said external test equipment to said memory device; and
inverting the test data transferred from said auxiliary memory circuit to said main memory circuit, responsive to said mode signal.

### Claim 13 (depends on 10)

The method of claim 10, further comprising the steps of:
sending a mode signal from said external test equipment to said memory device;
counting transfers of said test data from said auxiliary memory circuit to said main memory circuit, thereby generating a transfer count; and
inverting one bit in the test data transferred from said auxiliary memory circuit to said main memory circuit, responsive to said mode signal, said one bit being designated by said transfer count.

### Claim 14 (depends on 10)

The method of claim 10, wherein said memory device has an internal address counter, further comprising the steps of:
using said internal address counter to count transfers of said test data from said auxiliary memory circuit to said main memory circuit, thereby generating an address count; and
using said address count to designate said different locations in said main memory circuit.

### Claim 15 (depends on 10)

The method of claim 10, further comprising the steps of:
providing a comparator in said memory device;
reading data from said main memory circuit into said comparator; and
using said comparator to compare the data read from said main memory circuit with the test data stored in said auxiliary memory circuit.

### Claim 16

A test facilitation circuit integrated into a memory device having a main memory circuit with a plurality of memory cells, to facilitate testing of said main memory circuit by external test equipment, comprising:
a first auxiliary memory circuit storing test data;
an internal data bus coupling said first auxiliary memory circuit to said main memory circuit;
an interface circuit receiving address information, a read request signal, and a write request signal from said external test equipment, and transferring said test data to and from said external test equipment;
an auxiliary memory controller coupled to said interface circuit, controlling access to said first auxiliary memory circuit; and
a main memory controller coupled to said interface circuit, receiving a first test mode signal from said external test equipment, responding to said write request signal when said first test mode signal is in one state by directing said auxiliary memory controller to transfer said test data from said interface circuit to said first auxiliary memory circuit, and responding to said write request signal when said first test mode signal is another state by transferring test data immediately from said first auxiliary memory circuit to said main memory circuit;
wherein said auxiliary memory controller sends said main memory controller a status signal, indicating storage of said test data in said auxiliary memory, upon completion of transfer of said test data from said interface circuit to said first auxiliary memory circuit, and when said first test mode signal is in said one state, said main memory controller transfers said test data from said first auxiliary memory circuit to said main memory circuit responsive to said status signal.

### Claim 17

A method of testing a memory device having a main memory circuit, an auxiliary memory circuit, and an interface circuit, comprising the steps of:
sending address information, a first test mode signal, a read request signal, and a write request signal from external test equipment to said interface circuit;
when said first test mode signal is in a first state, and in response to said write request signal:
transferring test data from said external test equipment to said interface circuit;
storing said test data in said auxiliary memory circuit; and
transferring said test data from said auxiliary memory circuit to said main memory circuit; and
when said first test mode signal is in a second state, and in response to said write request signal:
transferring test data previously stored in said auxiliary memory circuit to said main memory circuit.