# US 6,295,593 B1 · Method of operating memory array with write buffers and related apparatus

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- Number: US 6,295,593 B1
- Document ID: US6295593B1
- Status: Granted
- Kind: B1
- Application number: 09/153,099
- Filed: 1998-09-14
- Granted: 2001-09-25
- Earliest claimed: 1995-05-17
- Assignees: Monolithic System Technology, Inc.
- Inventors: Fu-Chieh Hsu; Wingyu Leung
- Web page: https://patentgrep.com/patent/US6295593B1

## CPC

- G06F 12/0893: Caches characterised by their organisation or structure
- G06F 12/0855: Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence)
- G06F 12/0879: Burst mode
- G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
- G06F 12/10: Address translation
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 7/1018: {Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters}
- G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits}
- G11C 7/1069: {I/O lines read out arrangements}
- G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits}
- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- G11C 11/406: Management or control of the refreshing or charge-regeneration cycles
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and a second level cache memory which includes a DRAM array coupled to the CPU bus. When accessing the DRAM array, row access and column decoding operations are performed in a self-timed asynchronous manner. Predetermined sequences of column select operations are then performed in a synchronous manner with respect to a clock signal. A widened data path is provided to the DRAM array, effectively increasing the data rate of the DRAM array. By operating the DRAM array at a higher data rate than the CPU bus, additional time is provided for precharging the DRAM array. As a result, the precharging of the DRAM array is transparent to the CPU bus. A structure and method control the refresh and internal operations of the DRAM array.

## Claims

### Claim 1

A method of operating a memory array coupled to an external bus comprising:
providing a write buffer coupled between the external bus and the memory array;
transferring a first data set from the external bus into the write buffer during a write cycle at a first data transfer rate;
during the same write cycle, transferring a second data set transferred into the write buffer during a previous write cycle from the write buffer to the memory at a second data transfer rate greater than said first data transfer rate; and
performing a memory precharge operation on the memory during the time that the first data set is transferred from the external bus to the write buffer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the memory array is a dynamic random access memory (DRAM).

### Claim 3 (depends on 1)

The method of claim 1, further comprising;
clocking transfer of the first data set into the write buffer by a first clock signal associated with the bus; and
clocking transfer of the second data set out of the write buffer by a second clock signal associated with the memory array.

### Claim 4 (depends on 3)

The method of claim 3, wherein a frequency of the second clock signal is higher than that of the first clock signal.

### Claim 5

A computer system comprising:
a central processing unit (CPU);
at least one memory associated with the CPU;
a bus coupled to the CPU;
a memory coupled to the bus, the memory comprising at least one array; and
a write buffer coupled between the bus and the memory array;
wherein during a single write cycle of the write buffer a first data set is transferred from the bus into the write buffer at a first data transfer rate, a second data set transferred during a previous write cycle into the write buffer is transferred from the write buffer to the memory array at a second data rate greater than the first data rate, and a memory precharge operation is performed on the memory array during the time that the first data set is transferred from the external bus to the write buffer.

### Claim 6 (depends on 5)

The system of claim 5, wherein the memory array is a dynamic random access memory (DRAM).

### Claim 7 (depends on 5)

The system of claim 5, further comprising:
clocking transfer of the first data set into the write buffer by a first clock signal with the bus; and
clocking transfer of the second data set out of the write buffer by a second clock signal associated with the memory array.

### Claim 8 (depends on 5)

The system of claim 5, wherein a frequency of the second clock signal is higher than that of the first clock signal.