Method of processing memory requests in a pipelined memory controller
AssigneeMicron Technology, Inc.
InventorJoseph Jeddeloh
Life of this patent
Estimating the term…
Abstract
A method for processing multiple memory requests in a pipeline. Each memory request is processed in part by a plurality of stages. In a first stage, the memory request is decoded. In a second stage, the address information for the memory request is processed. In a third stage, the data for the memory request is transferred. A request buffer is used to hold each of the memory requests during the processing of each of the memory requests.
Claims18
A method of processing at least one memory request, comprising:
- processing the at least one memory request in a plurality of stages, wherein in a first stage, the at least one memory request is received from a memory requester and stored in a request buffer, wherein in a second stage the at least one memory request is decoded, wherein in a third stage the at least one memory request is sent to a memory module, and wherein in a fourth stage the data from the at least one memory request is communicated from the memory module to a data transfer module.
A method of manufacturing a pipelined memory controller, comprising:
- connecting a request queue having a plurality of registers to a state machine;
- assigning a request pointer to reference the most recent memory request in the request queue;
- and
- coupling a data transfer module, a decode module and a memory address module to the state machine, each of the modules having a pointer which points to a memory request in the request queue.
A method of pipelining memory requests in a memory controller, comprising:
- receiving a memory request from a processor;
- storing the memory request in a first register;
- pointing a request pointer to the first register;
- pointing a decode pointer to the first register;
- pointing an address pointer to the first register;
- decoding the address of the memory request in the first register;
- sending the address of the memory request to a memory module;
- receiving a second memory request;
- storing the second memory request in a second register;
- updating the request pointer to reference the second memory request;
- updating the decode pointer to reference the second memory request;
- updating the address pointer to reference the second memory request;
- decoding the address in the second memory address;
- incrementing the decode and address pointers;
- sending the address of the memory request to a memory module;
- and
- transferring the data requested by the first and second memory requests from the memory module to a data transfer module.
Dependencies are inferred from the claim text.