# US 6,295,590 B1 · Semiconductor memory apparatus having a protecting circuit

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- Number: US 6,295,590 B1
- Document ID: US6295590B1
- Status: Granted
- Kind: B1
- Application number: 08/353,254
- Filed: 1994-12-02
- Granted: 2001-09-25
- Earliest claimed: 1993-12-03
- Assignees: Rohm Col, Ltd.
- Inventors: Kyoji Marumoto
- Web page: https://patentgrep.com/patent/US6295590B1

## CPC

- G06F 12/1466: {Key-lock mechanism}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A semiconductor memory incorporates a protecting circuit which causes data, stored in a memory portion, to be output by executing a key canceling sequence from an external apparatus. The data stored in the memory are output only when a key canceling signal is input to the protecting circuit. Thus the data are not output only by inputting an address signal and a reading signal to the memory apparatus. As a result, it is impossible to find out the contents of the program stored in the memory portion without inputting the key canceling signal.

## Claims

### Claim 1

A semiconductor memory apparatus, comprising:
a memory portion storing a program;
a terminal for external connection;
a three-state buffer, one end of said three-state buffer is connected to said memory portion so that said three-state buffer can receive program data from said memory portion, and another end of said three-state buffer is connected to said terminal for external connection, said three-state buffer being capable of taking a high-impedance state in addition to two-value states of high-level and low-level;
a key memory for storing key data;
an input register, connected to said terminal for external connection, for storing a key release signal received via said terminal when said three-state buffer is in the high-impedance state;
an RS flip-flop connected to said three-state buffer, for turning said three-state buffer into the high-impedance state to disconnect said memory portion from said terminal under a reset state and for canceling the high-impedance state under a set state;
a power-on reset circuit for resetting said RS flip-flop when a power is turned on; and
a comparator for comparing an output from said key memory and an output from said input register to set said RS flip-flop when the two outputs coincide.

### Claim 2 (depends on 1)

A semiconductor memory apparatus as claimed in claim 1, wherein said key memory is connected to said terminal so that key data can be written into said key memory via said terminal when said three-state buffer is in the high-impedance state.

### Claim 3 (depends on 2)

A semiconductor memory apparatus as claimed in claim 2, further including an enable terminal for receiving an enable signal that enables key data to be written into said key memory.

### Claim 4 (depends on 3)

A semiconductor memory apparatus as claimed in claim 3, wherein said key memory is formed with a nonvolatile memory.