# US 6,295,572 B1 · Integrated SCSI and ethernet controller on a PCI local bus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,295,572 B1 - Document ID: US6295572B1 - Status: Granted - Kind: B1 - Application number: 08/186,050 - Filed: 1994-01-24 - Granted: 2001-09-25 - Earliest claimed: 1994-01-24 - Assignees: Advanced Micro Devices, Inc. - Inventors: Chih-Siung Wu - Web page: https://patentgrep.com/patent/US6295572B1 ## CPC - H03K 19/00361: {in field effect transistor circuits} - G06F 13/128: {for dedicated transfers to a network (for protocol converters G06F13/387)} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An integration of components of SCSI and Ethernet adapter boards onto a single chip forming an integrated Ethernet-SCSI controller for use on a PCI Local Bus. Integration is enabled by a reduction of noise. Noise is first reduced by reducing ground bounce by providing additional VSS pins for supporting large PCI and SCSI output buffers which constantly switch current. The VSS pins supporting the large PCI and SCSI output buffers support a limited number of output buffers located in a local area of the pin as connected to the pin by individual lines. Noise is additionally reduced by providing circuitry on the digital output buffers to limit the change of current over time (di/dt) during switching of the output buffers. Noise is further reduced by locating digital control circuitry so that current density increases in a direction away from analog circuitry. Finally, noise is reduced by including bidirectional silicon controlled rectifiers between power supplies in the analog portion, digital portion, and digital I/O buffer portion of the combined Ethernet-SCSI controller. ## Claims ### Claim 1 An apparatus comprising a SCSI controller and an Ethernet controller integrated onto a single integrated circuit chip, wherein the SCSI and Ethernet controller include digital control circuitry coupled to buffers, and the Ethernet controller includes analog circuitry, wherein circuitry on the integrated circuit chip is configured to limit noise generated in the analog circuitry by signals in the digital control circuitry, wherein the circuitry on the integrated circuit chip comprises VSS leads including a first set of VSS leads connected to the digital control circuitry and the analog circuitry and a second set of VSS leads connected only to the buffers. ### Claim 2 (depends on 1) The apparatus of claim 1 wherein the buffers comprise first and second buffers, wherein the first buffers are each connected to one of the second set of VSS leads by a line separate from the second buffers. ### Claim 3 An apparatus comprising a SCSI controller and an Ethernet controller integrated onto a single integrated circuit chip, wherein the SCSI and Ethernet controller include digital control circuitry coupled to buffers, and the Ethernet controller includes analog circuitry, wherein the circuitry on the integrated circuit chip is configured to limit noise generated in the analog circuitry by signals in the digital control circuitry, wherein the integrated circuit chip includes a data input for receiving a data signal and an output, wherein each of the buffers comprise: transistor pairs, each transistor pair having a pull up transistor and a pull down transistor, wherein each of the pull up transistors has a source to drain path connected between VDD and the buffer output, and wherein each of the pull down transistors has a source to drain path connected between VSS and the buffer output; and delay elements connected in series, wherein a first one of the delay elements has an input forming the data input of the buffer, and wherein each of the delay elements has an output coupled to a gate of each of the pull up and pull down transistors of one of the transistor pairs. ### Claim 4 An apparatus comprising a SCSI controller and an Ethernet controller integrated onto a single integrated circuit chip, wherein the SCSI and Ethernet controller include digital control circuitry coupled to buffers, and the Ethernet controller includes analog circuitry, wherein circuitry on the integrated circuit chip is configured to limit noise generated in the analog circuitry by signals in the digital control circuitry, wherein the analog circuitry is located separate from the digital control circuitry and the buffers. ### Claim 5 An apparatus comprising a SCSI controller and an Ethernet controller integrated onto a single integrated circuit chip, wherein the SCSI and Ethernet controller include digital control circuitry coupled to buffers, and the Ethernet controller includes analog circuitry, wherein circuitry on the integrated circuit chip is configured to limit noise generated in the analog circuitry by signals in the digital control circuitry, wherein current density in the digital control circuitry increases in a direction away from the analog circuitry. ### Claim 6 An apparatus comprising a SCSI controller and an Ethernet controller integrated onto a single integrated circuit chip, wherein the SCSI and Ethernet controller include digital control circuitry coupled to buffers, and the Ethernet controller includes analog circuitry, wherein circuitry on the integrated circuit chip is configured to limit noise generated in the analog circuitry by signals in the digital control circuitry, wherein the circuitry on the integrated circuit chip comprises: power distribution networks, including a first network connected to distribute power to the analog circuitry, a second network connected to distribute power to the digital control circuitry and a third network connected to distribute power to the buffers; and silicon control rectifiers (SCRs) connected between the power distribution networks, each SCR for sensing when a voltage difference between two of the power distribution networks exceeds a predefined limit, and for forming a conductive path between the two networks when the predefined limit is reached. ### Claim 7 An integrated circuit comprising: internal circuitry; buffers; and VSS leads including a first set of VSS leads connected to the internal circuitry and a second set of VSS leads connected only to the buffers. ### Claim 8 (depends on 7) The integrated circuit of claim 7 wherein the buffers comprise first and second buffers, wherein the first buffers are each connected to one of the second set of VSS leads by a line separate from the second buffers. ### Claim 9 (depends on 7) The integrated circuit of claim 7 wherein the first set of VSS leads comprises analog VSS leads and digital VSS leads and wherein the internal circuitry comprises: digital control circuitry connected to the digital VSS leads; and analog circuitry connected to the analog VSS leads.