# US 6,295,327 B1 · Method and apparatus for fast clock recovery phase-locked loop with training capability

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- Number: US 6,295,327 B1
- Document ID: US6295327B1
- Status: Granted
- Kind: B1
- Application number: 09/370,606
- Filed: 1999-08-10
- Granted: 2001-09-25
- Earliest claimed: 1996-10-17
- Assignees: Hitachi Micro Systems, Inc.
- Inventors: Ashraf K. Takla
- Web page: https://patentgrep.com/patent/US6295327B1

## CPC

- H03L 7/143: {by switching the reference signal of the phase-locked loop}
- H03L 7/101: {using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop (H03L7/113, H03L7/187 take precedence)}
- H03L 7/18: using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence)
- H04L 7/0004: {Initialisation of the receiver (H04L7/0075 and H04L7/10 take precedence)}
- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L 7/0331: {with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence)}
- H04L 7/10: Arrangements for initial synchronisation
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A phase-locked loop with training capability that reduces the time for clock recovery of a clock signal at a known frequency embedded in a data signal. Prior to the data signal being available, the phase-locked loop, in a training mode, acquires frequency and phase lock with a local oscillator signal. As a result, the output of the PLL is frequency locked substantially at the frequency of the clock embedded in the expected data signal. To achieve this result, in the training mode, the PLL compares the local oscillator signal divided by a first divider with the output clock signal divided by a second divider. Then the frequency of the output clock signal of the PLL equals the frequency of the local oscillator multiplied by the ratio of the divisor of the second divider over the divisor of the first divider. When the data signal is available, the PLL operates in a data receiving mode. In that mode, the PLL typically only needs to acquire phase lock, since frequency lock already has been acquired in the training mode.

## Claims

### Claim 1

A method for acquiring frequency and phase lock comprising:
receiving a local oscillator signal;
receiving an output clock signal;
modifying the output clock signal according to a function to generate a modified output clock signal;
causing a detector to compare the local oscillator signal with the modified output clock signal;
adjusting the frequency of the output clock signal based on the comparison between the modified output clock signal and the local oscillator signal to generate an adjusted output clock signal having a frequency substantially equal to an expected data signal frequency;
receiving a data signal having an actual data signal frequency substantially equal to the expected data signal frequency;
causing the detector to compare the phase of the data signal with the phase of the adjusted output clock signal; and
adjusting the adjusted output clock signal based on the comparison between the phase of the data signal with the phase of the adjusted output clock signal.

### Claim 2 (depends on 1)

The method of claim 1, wherein comparing the local oscillator signal with the modified output clock signal includes comparing the phase of the local oscillator signal with the phase of the modified output clock signal.

### Claim 3 (depends on 2)

The method of claim 2, further comprising adjusting the frequency of the adjusted output clock signal based on the comparison of the phase of the data signal with the phase of the output clock signal.

### Claim 4

A method for acquiring frequency and phase lock comprising:
selecting a local oscillator signal for input to a detector, the detector being coupled to a clock generator which provides an output clock signal;
adjusting the frequency of the output clock signal based on the frequency of the selected local oscillator signal to generate an adjusted output clock signal having a frequency substantially equal to an expected data signal frequency;
selecting a data signal for input to the detector, the selected data signal having a frequency substantially equal to the expected data signal frequency; and adjusting the phase of the adjusted output clock signal based on the phase of the selected data signal.

### Claim 5

The method of claims further comprising generating a control signal indicative of the availability of the data signal.