# US 6,295,242 B1 · SRAM with current-mode test read data path

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- Number: US 6,295,242 B1
- Document ID: US6295242B1
- Status: Granted
- Kind: B1
- Application number: 08/722,486
- Filed: 1996-09-27
- Granted: 2001-09-25
- Earliest claimed: 1992-09-09
- Assignees: Sony Electronics Inc.
- Inventors: Lee-Lean Shu; Kurt Knorpp; Katsunori Seno
- Web page: https://patentgrep.com/patent/US6295242B1

## CPC

- G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits}
- G11C 7/1069: {I/O lines read out arrangements}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A current sensing, cascadable differential amplifier has a special bias circuit that provides a low impedance input and a high impedance output, whereby plural stages may be connected in cascade. Optionally, active current sources are used as pull-ups for the data lines, to increase the output impedance and improve the data line common mode level. The amplifier performs as a current sensing sense amplifier in a large scale, fast access semiconductor means and in this application, the memory does not need equalizing clock signals, nor is the access time slowed materially in the plural cascade stages.

## Claims

### Claim 1

A semiconductor memory comprising a plurality of memory cells arranged in rows and columns and having a pair of bit lines for each column, and a two stage differential current sensing amplifier having a pair of input terminals connected to a pair of said bit lines, said differential current sensing amplifier having a pair of input transistors connected to said bit line pair and means for biasing said input transistors into conduction, whereby neither of said input transistors is cut off during reading or writing access to said memory at a time other than testing said memory.

### Claim 2 (depends on 1)

The semiconductor memory according to claim 1, wherein the bit lines of said semiconductor memory do not have means for equalizing the voltage on said bit lines.

### Claim 3

A semiconductor memory comprising a plurality of memory cells arranged in rows and columns at least one two stage differential current sensing amplifier having a pair of input terminals connected to a pair of bit lines, said differential current sensing amplifier having a pair of input transistors connected to said bit line pair and means for biasing said input transistors into conduction, and wherein neither of said input transistors is cut off during reading or writing access to said memory.

### Claim 4 (depends on 3)

The semiconductor memory of claim 3, wherein the means for biasing is comprised of a pair of transistors with gate electrodes connected to a voltage reference.