# US 6,295,238 B1 · Semiconductor memory device having a circuit for fast operation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,295,238 B1 - Document ID: US6295238B1 - Status: Granted - Kind: B1 - Application number: 09/604,007 - Filed: 2000-06-26 - Granted: 2001-09-25 - Earliest claimed: 1999-06-28 - Assignees: Mitsubishi Denki Kabushiki Kaisha - Inventors: Tetsushi Tanizaki; Katsumi Dosaka; Mikio Asakura - Web page: https://patentgrep.com/patent/US6295238B1 ## CPC - G11C 29/48: Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths - G11C 11/406: Management or control of the refreshing or charge-regeneration cycles - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of the command decoder. When the test signal is at H-level, the auto-refresh signal is issued in accordance with the output (external clock) of the clock buffer. Thereby, the test can be performed with a good timing accuracy even by a low-speed tester. ## Claims ### Claim 1 A semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in rows and columns, and a plurality of word lines arranged corresponding to the plurality of rows of said memory cells; a test mode detecting circuit detecting in accordance with an external signal the fact that a test mode is set; and a control circuit being responsive to the output of said test mode detecting circuit and triggered by an external clock to perform control for conducting a disturb test on said memory cell array, said external clock including a first external signal and a second external signal having the substantially same period as the first external signal. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein said semiconductor memory device further comprises an internal clock generator generating an internal clock based on a phase difference between said first and second external signals; and said control circuit performs the control for conducting said disturb test triggered by the internal clock. ### Claim 3 (depends on 1) The semiconductor memory device according to claim 1, wherein said second external signal has the different phase from the first external signal; said semiconductor memory device further comprises an internal clock generator generating an internal clock in accordance with said first and second external signals; and said control circuit performs the control for conducting said disturb test triggered by the internal clock. ### Claim 4 (depends on 3) The semiconductor memory device according to claim 3, wherein said internal clock has pulses corresponding to rising and falling edges of said first external signal. ### Claim 5 A semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in rows and columns, and a plurality of word lines arranged corresponding to the plurality of rows of said memory cells; a test mode detecting circuit detecting in accordance with an external signal the fact that a test mode is set; a control circuit being responsive to the output of said test mode detecting circuit and triggered by an external clock to perform control for conducting a disturb test on said memory cell array; a clock buffer for receiving said external clock; and a row select control circuit for controlling selection of the row in said memory cell array, wherein said control circuit is responsive to the output of said test mode detecting circuit to issue a signal determining operation timing of said row select control circuit based on the output of said clock buffer. ### Claim 6 (depends on 5) The semiconductor memory device according to claim 5, wherein said control circuit includes a refresh circuit issuing an automatic refresh signal for executing a refreshing operation of said memory cell array, and said refresh circuit operates in a normal operation to issue said automatic refresh signal in response to an external command, and operates in said test mode to issue said automatic refresh signal in synchronization with the output of said clock buffer. ### Claim 7 A semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in rows and columns, and a plurality of word lines arranged corresponding to the plurality of rows of said memory cells; a test mode detecting circuit detecting in accordance with an external signal the fact that a test mode is set; a control circuit being responsive to the output of said test mode detecting circuit and triggered by an external clock to perform control for conducting a disturb test on said memory cell array; a first buffer taking in said external clock, a second buffer taking in said external clock, and an internal clock generator generating an internal clock having double the frequency of said external clock in accordance with the outputs of said first and second buffers, wherein said control circuit performs the control for conducting said disturb test triggered by the internal clock. ### Claim 8 (depends on 7) The semiconductor memory device according to claim 7, wherein said first and second buffers have the substantially same characteristics, and said internal clock generator generates said internal clock having the substantially constant pulse width based on the outputs of said first and second buffers.