# US 6,295,224 B1 · Circuit and method of fabricating a memory cell for a static random access memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,295,224 B1 - Document ID: US6295224B1 - Status: Granted - Kind: B1 - Application number: 09/475,101 - Filed: 1999-12-30 - Granted: 2001-09-25 - Earliest claimed: 1999-12-30 - Assignees: STMicroelectronics S.r.l. - Inventors: Tsiu Chiu Chan; Mehdi Zamanian; David Charles McClure - Web page: https://patentgrep.com/patent/US6295224B1 ## CPC - H10B 10/00: Static random access memory [SRAM] devices - G11C 11/412: using field-effect transistors only - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A circuit and method is disclosed for a memory cell for a static random access memory. The memory cell includes a pair of cross-coupled CMOS logic inverters that are connected together to form a latch, and a pair of p-channel transmission gate transistors that are connected to the logic inverters for selectively providing access to the latch. The layout of the memory cell includes a rectangular active area in which the p-channel transistors of the memory cell are located. The rectangular active area abuts a similar active area of an adjacent memory cell along a row of memory cells so as to form a single rectangular active area for the p-channel memory cell transistors. The rectangular active area reduces the occurrence of fabrication-related phenomena that adversely effect the performance of the memory cell. ## Claims ### Claim 1 A memory cell for a static random access memory (SRAM) device fabricated on a semiconductor substrate, comprising: a first logic inverter; a second logic inverter cross-coupled to the first logic inverter, the first logic inverter and the second logic inverter each comprise a p-channel pull-up transistor; a first p-channel transistor having a gate terminal connected to a word line of the SRAM device, a first source/drain terminal connected to a first bit line of a bit line pair of the SRAM device and a second source/drain terminal connected to an output of the first logic inverter; and a second p-channel transistor having a gate terminal connected to the word line of the SRAM device, a first source/drain terminal connected to a second bit line of the bit line pair and a second source/drain terminal connected to an output of the second logic inverter, the first and second p-channel transistors and the p-channel pull-up transistors are defined within a single active area, the active area having a substantially rectangular shape. ### Claim 2 (depends on 1) The memory cell of claim 1, wherein: the first logic inverter comprises an n-channel pull-down transistor; and the ratio of the width-to-length ratio of the n-channel pull-down transistor of the first logic inverter to the width-to-length ratio of the first p-channel transistor is approximately between 1.0 and 1.5. ### Claim 3 (depends on 1) The memory cell of claim 1, wherein: the first logic inverter comprises a p-channel pull-up transistor; and the first p-channel transistor and the p-channel pull-up transistor have approximately the same channel size. ### Claim 4 (depends on 1) The memory cell of claim 1, wherein: the active area of the first and second p-channel transistors and the p-channel pull-up transistors abuts a corresponding active area of adjacent memory cells in a first direction on the semiconductor material to form a single substantially rectangular active area. ### Claim 5 (depends on 1) The memory cell of claim 1, wherein: the first inverter comprises an n-channel pull-down transistor; and the ratio of the transistor gain factor of the n-channel pull-down transistor to the transistor gain factor of the second p-channel transistor is approximately between 2.0 and 3.0. ### Claim 6 A memory cell for a static random access memory (SRAM) device fabricated on a semiconductor substrate, comprising: a first logic inverter; a second logic inverter cross-coupled to the first logic inverter; a first p-channel transistor having a gate terminal connected to a word line of the SRAM device, a first source/drain terminal connected to a first bit line of a bit line pair of the SRAM device and a second source/drain terminal connected to an output of the first logic inverter; and a second p-channel transistor having a gate terminal connected to the word line of the SRAM device, a first source/drain terminal connected to a second bit line of the bit line pair and a second source/drain terminal connected to an output of the second logic inverter; wherein the first logic inverter and the second logic inverter each comprise a n-channel pull-down transistor; and the n-channel pull-down transistors are defined within a single active area, the active area having a substantially rectangular shape. ### Claim 7 A static random access memory device defined over a semiconductor substrate, comprising: one or more rows of memory cells, each memory cell comprising two p-channel pull-up transistors, two p-channel pass gate transistors and two n-channel pull-down transistors that are connected to the p-channel pull-up transistors to form a pair of cross-coupled inverters, each row of memory cells comprising: a substantially rectangular first active area in which the p-channel pull-up transistors and p-channel pass gate transistors are located; and a plurality of second active areas in which the n-channel transistors are located, each active area having n-channel transistors for a single memory cell located therein; address circuitry for selecting a memory cell; and control circuitry for selectively reading data from and writing data into the selected memory cell. ### Claim 8 (depends on 7) The static random access memory device of claim 7, wherein: for each memory cell, each p-channel pass gate transistor is connected to a drain terminal of a distinct n-channel pull-down transistor, a ratio of the width-to-length ratio of a n-channel pull-down transistor to the ratio of the corresponding p-channel pass gate transistors is approximately between 1.0 and 1.5. ### Claim 9 (depends on 7) The static random access memory device of claim 7, wherein: for each memory cell, each p-channel pass gate transistor is connected to a drain terminal of a distinct p-channel pull-up transistor of the memory cell, a ratio of the width-to-length ratio of each p-channel pull-up transistor to the corresponding p-channel pass gate transistor is approximately 1.0. ### Claim 10 (depends on 7) The static random access memory device of claim 7, wherein: for each memory cell, control gate electrodes of the p-channel pull-up transistors and p-channel pass gate transistors are formed by polysilicon segments that are substantially parallel to each other. ### Claim 11 (depends on 7) The static random access memory device of claim 7, wherein: each of the second active areas is substantially rectangular. ### Claim 12 (depends on 7) The static random access memory device of claim 7, wherein: for each memory cell, control gate electrodes of the p-channel pull-up transistors and p-channel pass gate transistors are formed by polysilicon segments that are substantially orthogonal to a longitudinal direction of the first active area. ### Claim 13 (depends on 7) The static random access memory device of claim 7, wherein: the p-channel pull-up transistors, the p-channel pass gate transistors and the n-channel pull-down transistors are MOSFET transistors. ### Claim 14 A static random access memory device defined over a semiconductor substrate, comprising: one or more rows of memory cells, each memory cell comprising two p-channel pull-up transistors, two p-channel pass gate transistors and two n-channel pull-down transistors that are connected to the p-channel pull-up transistors to form a pair of cross-coupled inverters, each row of memory cells comprising: one or more substantially rectangular first active areas in which the p-channel pull-up transistors and p-channel pass gate transistors in the row are located; and one or more substantially rectangular second active areas in which the n-channel pull-down transistors in the row are located; address circuitry for selecting a memory cell; and control circuitry for selectively reading data from and writing data into the selected memory cell. ### Claim 15 (depends on 14) The static random access memory device of claim 14, wherein: each row of memory cells includes a plurality of substantially rectangular first active areas in which the p-channel pull-up transistors and p-channel pass gate transistors in the row are located. ### Claim 16 (depends on 14) The static random access memory device of claim 14, wherein: each row of memory cells includes a single substantially rectangular first active area in which the p-channel pull-up transistors and p-channel pass gate transistors in the row are located. ### Claim 17 (depends on 14) The static random access memory device of claim 14, wherein: for each memory cell, control gate electrodes of the p-channel pull-up transistors and p-channel pass gate transistors are formed by segments of polycrystalline material that are substantially parallel to each other. ### Claim 18 (depends on 14) The static random access memory device of claim 14, wherein: each of the one or more substantially rectangular first active areas in a row has disposed therein p-channel pull-up transistors and p-channel pass gate transistors corresponding to one or more memory cells. ### Claim 19 (depends on 14) The static random access memory device of claim 14, wherein: for each memory cell, control gate electrodes of the p-channel pull-up transistors and p-channel pass gate transistors are formed by segments that are substantially orthogonal to a longitudinal direction of the first active area for the memory cell. ### Claim 20 (depends on 14) The static random access memory device of claim 14, wherein: the p-channel pull-up transistors, the p-channel pass gate transistors and the n-channel pull-down transistors are MOSFET transistors.