Method and apparatus for self correcting parallel I/O circuitry
AssigneeLSI Logic Corporation
InventorsHarold S. Crafts, David P. Steele
Life of this patent
Estimating the term…
Abstract
3An optimal delay value, usually the mid-delay in the operational window, for the data signal may be retained as a way of shifting the skew of the clock on all data lines at the same time. That delay value may be stored in a memory and converted to a control voltage for controlling a digitally controlled voltage variable delay to adjust the delay for data in a bus. The digitally controlled voltage variable delay contains a number of individual delay units which are selectively activated by the control voltage from the value stored in memory. A phase locked loop is employed to ensure that variations due to voltage, temperature, and processing are minimized.
Claims22
A variable delay circuit for delaying bus signal timing comprising:
- a phase locked loop, wherein the phase locked loop generates a control signal;
- and
- a variable delay element connected to a bus line for delaying a signal on the bus line and further connected to the phase lock loop, wherein the control signal from the phase locked loop controls the variable delay element and stabilizes bus signal timing delays.
A variable delay circuit for delaying bus signal timing comprising:
- a memory for storing a value related to an initial number of active delay units;
- a logic element for selecting at least one of a plurality of delay units to activate, the logic element being connected to the memory, wherein the value related to an initial number of active delay units is used by the logic element to select at least one of the plurality of delay units to activate;
- and
- a bus carrying a data signal connected to a variable delay element containing the plurality of delay units, wherein the active units delay the signal timing of the bus.
A variable delay circuit for delaying bus signal timing on a plurality of bus lines comprising:
- connect to each bus line, a variable delay circuit comprising
- a plurality of delay units;
- a logic element for selecting at least one of the plurality of delay units to activate;
- and
- a memory for storing a value, wherein the value is used by the logic element for adjusting bus signal timing delay within operational limits of the bus by activating at least one logic element.
A method for delaying bus signal timing using a variable delay circuit, the method comprising:
- generating a stabilization signal in a phase locked loop;
- generating a control signal;
- stabilizing bus signal timing delays from a variable delay element connected to a bus line for delaying a signal on the bus line using the stabilization signal, and
- controlling bus signal timing delays from a variable delay element connected to the bus line for delaying a signal on the bus line using the control signal.
A method for delaying bus signal timing using a variable delay circuit, the method comprising:
- storing a value related to an initial number of active delay elements in a memory;
- and
- selecting at least one of the plurality of delay units to activate using a logic element, wherein the value related to a initial number of active delay units is used by the logic element to activate at least one of the plurality of delay units.
A method for delaying bus signal timing using a variable delay circuit, the method comprising:
- connecting to each bus line a variable delay circuit;
- for each bus line:
- delaying a signal using a plurality of delay units;
- selecting at least one of the plurality of delay units to activate using a logic element;
- reading a value from memory;
- and
- activating at least one delay element using the value, wherein the value is used by the logic element for adjusting bus signal timing delay within operational limits of the bus.
Dependencies are inferred from the claim text.