# US 6,294,936 B1 · Spread-spectrum modulation methods and circuit for clock generator phase-locked loop > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,294,936 B1 - Document ID: US6294936B1 - Status: Granted - Kind: B1 - Application number: 09/161,969 - Filed: 1998-09-28 - Granted: 2001-09-25 - Earliest claimed: 1998-09-28 - Assignees: American Microsystems, Inc. - Inventors: Daniel M. Clementi - Web page: https://patentgrep.com/patent/US6294936B1 ## CPC - H03C 3/095: {applying frequency modulation to the loop in front of the voltage controlled oscillator} - H03K 23/54: Ring counters, i.e. feedback shift register counters (H03K23/52 takes precedence) - H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) - H03L 7/18: using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) - H03K 3/84: Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators - H03C: MODULATION (masers or lasers H01S; coding, decoding or code conversion H03M) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract A spread-spectrum modulation method and circuit for a clock generator phase-locked loop (PLL). A dither signal is injected into a PLL in synchronization with and having the same period or fraction of the same period as the phase comparison performed within the PLL. Over such period, the phase error caused by the modulation will integrate to zero and hence avoid transmitting a disturbance to the loop. A particular embodiment utilizes an output of the reference divider and/or feedback divider within the PLL to generate the dither signal. Such a configuration avoids the need for additional hardware which otherwise would increase the chip area and/or cost of the device. The reference divider and/or feedback divider is made up preferably of a linear feedback shift register (LFSR). One or more stages of the LFSR provide an output which is used to generate the dither signal. In a preferred embodiment, the output from the LFSR exhibits a pseudo-random sequence. ## Claims ### Claim 1 A clock generator phase-locked loop, comprising: a reference frequency source for providing a reference frequency; a phase comparator for producing a control signal based on a periodic comparison of a phase difference between respective signals provided to a first input and a second input of the phase comparator, the reference frequency being operatively coupled to the first input; a voltage-controlled oscillator for generating an output frequency based on the control signal provided by the phase comparator; a feedback divider which receives and divides the output frequency to provide a divider output which is operatively coupled to the second input of the phase comparator; and a modulation circuit for injecting a dither signal into the control signal provided by the phase comparator to modulate the output frequency, a period of the dither signal being equal to or an integer fraction of a phase comparison period of the phase comparator. ### Claim 2 (depends on 1) The clock generator phase-locked loop of claim 1, wherein the period of the dither signal is equal to the phase comparison period. ### Claim 3 (depends on 1) The clock generator phase-locked loop of claim 1, wherein the feedback divider comprises a counter and the modulation circuit comprises a look-up table having modulation values stored therein for producing the dither signal, the value of the counter serving to provide a sequence of addresses to the look-up table for accessing the modulation values. ### Claim 4 (depends on 1) The clock generator phase-locked loop of claim 1, wherein the feedback divider comprises a counter and an output of the counter is used by the modulation circuit to produce the dither signal. ### Claim 5 (depends on 4) The clock generator phase-locked loop of claim 4, wherein the counter is a linear feedback shift register counter having a plurality of stages, and an output of at least one of the plurality of stages is used to produce the dither signal. ### Claim 6 (depends on 5) The clock generator phase-locked loop of claim 5, wherein the output of the at least one of the plurality of stages exhibits a pseudo-random sequence. ### Claim 7 (depends on 1) The clock generator phase-locked loop of claim 1, further comprising a reference divider for dividing an input reference frequency to produce the reference frequency. ### Claim 8 (depends on 7) The clock generator phase-locked loop of claim 7, wherein at least one of the reference divider and the feedback divider comprises a counter and the modulation circuit comprises a look-up table having modulation values stored therein for producing the dither signal, the value of the counter serving to provide a sequence of addresses to the look-up table for accessing the modulation values. ### Claim 9 (depends on 7) The clock generator phase-locked loop of claim 7, wherein at least one of the reference divider and the feedback divider comprises a counter and an output of the counter is used by the modulation circuit to produce the dither signal. ### Claim 10 (depends on 9) The clock generator phase-locked loop of claim 9, wherein the counter is a linear feedback shift register counter having a plurality of stages, and an output of at least one of the plurality of stages is used to produce the dither signal. ### Claim 11 (depends on 10) The clock generator phase-locked loop of claim 10, wherein the output of the at least one of the plurality of stages exhibits a pseudo-random sequence. ### Claim 12 A clock generator phase-locked loop, comprising: a reference frequency source for proving a reference frequency; a phase comparator for producing a control signal based on a phase difference between respective signals provided to a first input and a second input of the phase comparator, the reference frequency being operatively coupled to the first input; a voltage-controlled oscillator for generating an output frequency based on the control signal provided by the phase comparator; a feedback divider which receives and divides the output frequency to provide a divider output which is operatively coupled to the second input of the phase comparator; and a modulation circuit for injecting a dither signal within the clock generator phase-locked loop to modulate the output frequency, wherein at least one of a reference divider included in the reference frequency source and the feedback divider comprises a linear feedback shift register counter having a plurality of stages, and the modulation circuit receives an output of at least one of the plurality of stages which is used to produce the dither signal. ### Claim 13 (depends on 12) The clock generator phase-locked loop of claim 12, wherein the modulation circuit comprises at least one of a digital-to-analog converter which converts the output to an analog signal which serves to modulate the control signal, and means for capacitively coupling the output to a modulator included within the modulation circuit to modulate the control signal. ### Claim 14 (depends on 12) The clock generator phase-locked loop of claim 12, wherein the output exhibits a pseudo-random sequence. ### Claim 15 A method for dithering a clock generator phase-locked loop including a reference frequency source for providing a reference frequency, a phase comparator for producing a control signal based on a periodic comparison of a phase difference between respective signals provided to a first input and a second input of the phase comparator, the reference frequency being operatively coupled to the first input, a voltage-controlled oscillator for generating an output frequency based on the control signal provided by the phase comparator, and a feedback divider which receives and divides the output frequency to provide a divider output which is operatively coupled to the second input of the phase comparator, the method comprising the step of: injecting a dither signal into the control signal provided by the phase comparator to modulate the output frequency, a period of the dither signal being equal to or an integer fraction of a phase comparison period of the phase comparator. ### Claim 16 (depends on 15) The method of claim 15, wherein the period of the dither signal is equal to the phase comparison period of the phase comparator. ### Claim 17 (depends on 15) The method of claim 15, wherein the feedback divider comprises a counter and the injecting step comprises using a look-up table having modulation values stored therein for producing the dither signal, the value of the counter serving to provide a sequence of addresses to the look-up table for accessing the modulation values. ### Claim 18 (depends on 15) The method of claim 15, wherein the feedback divider comprises a counter and an output of the counter is used to produce the dither signal. ### Claim 19 (depends on 18) The method of claim 18, wherein the counter is a linear feedback shift register counter having a plurality of stages, and an output made up of at least one of the plurality of stages is used to produce the dither signal. ### Claim 20 (depends on 19) The method of claim 19, wherein the output of the at least one of the plurality of stages exhibits a pseudo-random sequence. ### Claim 21 (depends on 15) The method of claim 15, wherein the clock generator phase-locked loop further comprises a reference divider for dividing an input reference frequency to produce the reference frequency. ### Claim 22 (depends on 21) The method of claim 21, wherein at least one of the reference divider and the feedback divider comprises a counter and the injecting step comprises using a look-up table having modulation values stored therein for producing the dither signal, the value of the counter serving to provide a sequence of addresses to the look-up table for accessing the modulation values. ### Claim 23 (depends on 21) The method of claim 21, wherein at least one of the reference divider and the feedback divider comprises a counter and an output of the counter is used to produce the dither signal. ### Claim 24 (depends on 23) The method of claim 23, wherein the counter is a linear feedback shift register counter having a plurality of stages, and an output made up of at least one of the plurality of stages is used to produce the dither signal. ### Claim 25 (depends on 24) The method of claim 24, wherein the output of the at lease one of the plurality of stages exhibits a pseudo-random sequence. ### Claim 26 A method for dithering a clock generator phase-locked loop including a reference frequency source for proving a reference frequency, a phase comparator for producing a control signal based on a phase difference between respective signals provided to a first input and a second input of the phase comparator, the reference frequency being operatively coupled to the first input, a voltage-controlled oscillator for generating an output frequency based on the control signal provided by the phase comparator, and a feedback divider which receives and divides the output frequency to provide a divider output which is operatively coupled to the second input of the phase comparator, wherein at least one of a reference divider included in the reference frequency source and the feedback divider comprises a linear feedback shift register counter having a plurality of stages, the method comprising the step of: injecting a dither signal within the clock generator phase-locked loop to modulate the output frequency, the dither signal being based on an output of at least one of the plurality of stages. ### Claim 27 (depends on 26) The method of claim 26, wherein the injecting step comprises using an digital-to-analog converter which converts the output to an analog signal which serves to modulate the control signal. ### Claim 28 (depends on 26) The method of claim 26, wherein the injecting step comprises capacitively coupling the output to a modulator used to modulate the control signal. ### Claim 29 (depends on 26) The method of claim 26, wherein the output exhibits a pseudo-random sequence.