# US 6,294,835 B1 · Self-aligned composite insulator with sub-half-micron multilevel high density electrical interconnections and process thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,294,835 B1 - Document ID: US6294835B1 - Status: Granted - Kind: B1 - Application number: 09/365,684 - Filed: 1999-08-02 - Granted: 2001-09-25 - Earliest claimed: 1997-10-08 - Assignees: International Business Machines Corporation - Inventors: Hormazdyar M. Dalal; Du Binh Nguyen; Hazara S. Rathore - Web page: https://patentgrep.com/patent/US6294835B1 ## CPC - H10W 20/42: Vias, e.g. via plugs - H10W 20/071: {of dielectric parts thereof} - H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)} - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The present invention relates generally to a new sequence of methods and materials to improve the process yield and to enhance the reliability of multilevel interconnection with sub-half-micron geometry by making judicious use of composite insulators to prevent metal thinning over hard metal via plugs and by preventing process induced metal spike formation. The method takes advantage of the double damascene process. The metal spikes and the metal thinning resulting from over etch process is prevented in this method by using a pair of insulators which require different chemistries for etching. ## Claims ### Claim 1 A semiconductor substrate having at least one high electrical conductivity interconnect, wherein said substrate comprising at least one p/n junction in electrical contact with a metallic via-plug, at least one first insulator layer over said semiconductor substrate and surrounding said first metallic via-plug, at least a portion of at least one first level of high electrical conductivity interconnection line in contact with said first metallic via-plug, wherein a second and a third insulator layers are over said first insulator layer and surrounds said first level electrical interconnection line, at least a portion of at least one second level electrical interconnection line in contact with said first level electrical interconnection line through at least one high electrical conductivity via-plug, wherein at least a fourth and a fifth insulator layers are over said third insulator layer and surrounds said second level electrical interconnection line, and wherein each adjoining insulator layer is of a different material, and thereby forming said semiconductor substrate having at least one high electrical conductivity interconnect. ### Claim 2 (depends on 1) The substrate of claim 1, wherein material for said first high electrical conductivity interconnection line is the same as material for said second high electrical conductivity interconnection line. ### Claim 3 (depends on 1) The substrate of claim 1, wherein material for said first high electrical conductivity interconnection line is different than the material for said second high electrical conductivity interconnection line. ### Claim 4 (depends on 1) The substrate of claim 1, wherein said first and/or second high electrical conductivity interconnection line comprises of at least one layer of a contact metal, a barrier metal and a high conductivity metal. ### Claim 5 (depends on 4) The substrate of claim 4, wherein said at least one contact metal is selected from a group consisting of tantalum, titanium or alloys thereof. ### Claim 6 (depends on 4) The substrate of claim 4, wherein said barrier material is selected from a group consisting of chromium, chromium/chromium-oxide, cobalt, nickel, palladium, platinum, tantalum, tantalum-nitride, titanium-boride, titanium-nitride, titanium-oxy-nitride, titanium-silicide, titanium-tungsten, tungsten, tungsten-nitride, tungsten-silicon and alloys thereof. ### Claim 7 (depends on 4) The substrate of claim 4, wherein at least one of said first and/or second high conductivity metal is selected from a group consisting of aluminum, aluminum-copper, copper, copper-hafnium, copper-indium, copper-lanthanum, copper-tin, copper-zirconium, gold, silver, and alloys thereof. ### Claim 8 (depends on 4) The substrate of claim 4, wherein said first and/or second high electrical conductivity interconnection has at least one cap layer, and wherein said cap layer is selected from a group consisting of chromium, tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, tungsten-silicon, and alloys thereof. ### Claim 9 (depends on 1) The substrate of claim 1, wherein said at least one metallic via-plug is substantially in coplanarity with said at least one insulator layer. ### Claim 10 (depends on 1) The substrate of claim 1, wherein material for said third and/or fifth insulator is selected from a group consisting of aluminum-oxide, magnesium-oxide, phospho-silicate glass, polyimide, silicon-nitride, silicon-oxide, yttrium-oxide, flowable oxide and diamond like dielectric. ### Claim 11 (depends on 1) The substrate of claim 1, wherein material for said second and/or fourth insulator layer is selected from a group consisting of aluminum-oxide, magnesium-oxide, phospho-silicate glass, polyimide, silicon-nitride, silicon-oxide and yttrium-oxide. ### Claim 12 (depends on 1) The substrate of claim 1, wherein material for said metallic via-plug is selected from a group consisting of aluminum, chromium, chromium/chromium-oxide, cobalt, copper, molybdenum, nickel, palladium, platinum, tantalum, tantalum-nitride, titanium, titanium-boride, titanium-nitride, titanium-oxy-nitride, titanium-silicide, titanium-tungsten, tungsten, tungsten-nitride, tungsten-silicon, and alloys thereof.