# US 6,294,816 B1 · Secure integrated circuit

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 6,294,816 B1
- Document ID: US6294816B1
- Status: Granted
- Kind: B1
- Application number: 09/087,748
- Filed: 1998-05-29
- Granted: 2001-09-25
- Earliest claimed: 1992-07-31
- Assignees: Hughes Electronics Corporation
- Inventors: James P. Baukus; William M. Clark, Jr.; Lap-Wai Chow; Allan R. Kramer
- Web page: https://patentgrep.com/patent/US6294816B1

## CPC

- H10W 42/40: protecting against tampering, e.g. unauthorised inspection or reverse engineering
- G11C 7/24: Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
- H10D 89/00: Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An integrated circuit is protected from reverse engineering by connecting doped circuit elements of like conductivity with a doped implant in the substrate, rather than with a metallized interconnect. The doped circuit elements and their corresponding implant interconnections can be formed in a common fabrication step with common implant masks, such that they have an integral structure with similar dopant concentrations. The metallization above the substrate surface can be designed to provide further masking of the interconnects, and microbridges can be added to span strips of transistor gate material in the interconnect path.

## Claims

### Claim 1

A security system protected against reverse engineering, comprising:
a substrate;
at least one integrated circuit embedded in said substrate, said integrated circuit comprising:
a semiconductor substrate;
at least two logic circuits of different types formed in said semiconductor substrate with layouts which make said two logic circuits look alike to a reverse engineer, each logic circuit having doped IC elements, and
an interconnect for at least one of said elements, said interconnect comprising a dopant implant in said substrate of like conductivity to said element, and providing an electrical signal path to interconnect said element with another portion of the IC, said dopant implant being substantially not discernible by reverse engineering techniques.