# US 6,294,812 B1 · High density flash memory cell

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- Number: US 6,294,812 B1
- Document ID: US6294812B1
- Status: Granted
- Kind: B1
- Application number: 09/306,119
- Filed: 1999-05-06
- Granted: 2001-09-25
- Earliest claimed: 1999-05-06
- Assignees: United Microelectronics Corp.
- Inventors: Yen-Lin Ding; Gary Hong
- Web page: https://patentgrep.com/patent/US6294812B1

## CPC

- H10B 41/30: characterised by the memory core region
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A flash memory cell. A spacer is formed on a sidewall of a controlling gate. A self-aligned source/drain region can thus be formed by the formation of the spacer. The tunneling oxide layer is then formed on the source/drain region instead of on the controlling gate. Thus, the tunneling oxide layer is formed with a self-aligned process.

## Claims

### Claim 1

A flash memory cell, comprising:
a substrate;
a shallow trench isolation;
a drain region and a source region adjacent to the shallow trench isolation in the substrate;
a channel region between the drain region and the source region in the substrate;
a gate oxide layer over the channel region;
a tunneling layer covering the source region and the drain region;
a floating gate, on the gate oxide layer and the tunneling layer;
a dielectric layer, on the floating gate; and
a controlling gate, on the dielectric layer.

### Claim 2 (depends on 1)

The flash memory cell according to claim 1, wherein the substrate comprises a well.

### Claim 3 (depends on 1)

The flash memory cell according to claim 1, wherein the source region and the drain region include N-type doped regions.

### Claim 4 (depends on 1)

The flash memory cell according to claim 1, wherein source and drain regions include P-type doped regions.

### Claim 5 (depends on 1)

The flash memory cell according to claim 1, the tunneling layer comprises a silicon oxide layer.

### Claim 6 (depends on 1)

The flash memory cell according to claim 1, wherein the gate oxide layer has a thickness of about 70 to 200 Å.

### Claim 7 (depends on 1)

The flash memory cell according to claim 1, wherein the tunneling layer has a thickness of about 50 to 70 Å.

### Claim 8 (depends on 1)

The flash memory cell according to claim 1, wherein each of the source region and the drain region has a width ranged between 500 to 2000 Å.

### Claim 9 (depends on 1)

The flash memory cell according to claim 1, wherein the gate oxide layer has a width of about 0.1 to 0.5 μm.

### Claim 10 (depends on 1)

The flash memory cell according to claim 1, wherein the floating gate includes a polysilicon layer.

### Claim 11 (depends on 1)

The flash memory cell according to claim 1, wherein the controlling gate includes a polysilicon layer.

### Claim 12 (depends on 1)

The flash memory cell according to claim 1, wherein the dielectric layer includes an oxide/nitride/oxide layer.

### Claim 13

A flash memory cell, comprising:
a substrate;
a plurality pairs of doped regions in the substrate, each pair of the doped region being isolated by a shallow trench isolation;
a channel region, between two doped regions of each pair in the substrate;
a gate oxide layer, on the channel region on the substrate;
a tunneling layer, covering each pair of the doped region;
a first polysilicon layer, covering the tunneling layer and the gate oxide layer;
a dielectric layer, covering the first polysilicon layer; and
a second polysilicon layer, covering the dielectric layer.

### Claim 14 (depends on 13)

The flash memory according to claim 13, wherein the doped regions comprise a plurality of N-type doped regions.

### Claim 15 (depends on 13)

The flash memory according to claim 13, wherein doped regions comprise a plurality of P-type doped regions.

### Claim 16 (depends on 13)

The flash memory according to claim 13, wherein the shallow trench isolation has a depth deeper than the doped regions.

### Claim 17 (depends on 13)

The flash memory according to claim 13, wherein the gate oxide layer has a thickness of about 50 to 200 Å.

### Claim 18 (depends on 13)

The flash memory according to claim 13, wherein the gate oxide layer has a length of about 0.1 to 0.5 μm.

### Claim 19 (depends on 13)

The flash memory according to claim 13, wherein the tunneling layer has a thickness of about 50 to 70 Å.

### Claim 20 (depends on 13)

The flash memory according to claim 13, wherein each of the doped region has a length of about 500 to 2000 Å.

### Claim 21 (depends on 13)

The flash memory according to claim 13, wherein the first polysilicon layer has an island or block shape on the gate oxide layer and the tunneling layer.

### Claim 22 (depends on 13)

The flash memory according to claim 13, wherein the second polysilicon layer extends along a direction approximately perpendicular to a direction which the shallow trench isolation extends along.