# US 6,294,810 B1 · EEPROM cell with tunneling at separate edge and channel regions

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- Number: US 6,294,810 B1
- Document ID: US6294810B1
- Status: Granted
- Kind: B1
- Application number: 09/218,987
- Filed: 1998-12-22
- Granted: 2001-09-25
- Earliest claimed: 1998-12-22
- Assignees: Vantis Corporation
- Inventors: Xiao-Yu Li; Steven J. Fong
- Web page: https://patentgrep.com/patent/US6294810B1

## CPC

- G11C 16/0441: {comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates}
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

An EEPROM cell is described that is programmed and erased by electron tunneling at separate regions, an edge of a tunneling drain and a sense transistor channel. The EEPROM cell has three transistors formed in a semiconductor substrate. The three transistors are a tunneling transistor (NMOS), a sense transistor (NMOS) and a read transistor (NMOS). Electron tunneling occurs to program the EEPROM cell through a sense tunnel oxide layer by electron tunneling across an entire portion of a sense channel upon incurrence of a sufficient voltage potential between a floating gate and the sense channel. Electron tunneling also occurs to erase the EEPROM cell through a tunnel oxide layer be electron tunneling at an edge of a tunneling drain upon incurrence of a sufficient voltage potential between the floating gate and the tunneling drain.

## Claims

### Claim 1

An EEPROM cell, comprising:
a semiconductor substrate, said semiconductor substrate having a first conductivity type;
a tunneling transistor formed in said semiconductor substrate, said tunneling transistor having a tunneling source, a tunneling drain and a tunneling channel between said tunneling source and said tunneling drain, said tunneling drain and said tunneling source having a second conductivity type that is opposite said first conductivity type;
a tunnel oxide layer overlying said tunneling channel, said tunneling source and said tunneling drain;
a program junction region formed in said semiconductor substrate, said program junction region separated from said tunneling transistor by a first oxide, said program junction region having said second conductivity type;
a program junction oxide layer overlying said program junction region;
a sense transistor formed in said semiconductor substrate and separated from said program junction region by a second oxide, said sense transistor having a sense source, a sense drain and a sense channel between said sense source and said sense drain, said sense source and said sense drain having said second conductivity type;
a sense tunnel oxide layer overlying said sense channel, said sense source and said sense drain;
a read transistor formed in said semiconductor substrate, said read transistor having a read source and a read drain, said read transistor electrically coupled to said sense transistor through said sense drain; and
a floating gate overlying said tunnel oxide layer, said program junction oxide layer and said sense tunnel oxide layer, wherein electron tunneling through said tunnel oxide layer overlying an edge of said tunneling drain occurs upon incurrence of a sufficient voltage potential between said floating gate and said tunneling drain, and wherein electron tunneling through said sense tunnel oxide layer overlying said sense channel occurs upon incurrence of a sufficient voltage potential between said floating gate and said sense channel.

### Claim 2 (depends on 1)

The EEPROM cell of claim 1, wherein said first conductivity type is a P type conductivity.

### Claim 3 (depends on 2)

The EEPROM cell of claim 2, wherein said second conductivity type is an N type conductivity.

### Claim 4 (depends on 1)

The EEPROM cell of claim 1, wherein said electron tunneling through said sense tunnel oxide layer overlying said sense channel occurs across an entire portion of said sense channel.

### Claim 5 (depends on 1)

The EEPROM cell of claim 1, wherein said electron tunneling through said tunnel oxide layer overlying said edge of said tunneling drain only erases said EEPROM cell.

### Claim 6 (depends on 1)

The EEPROM cell of claim 1, wherein said electron tunneling through said sense tunnel oxide layer only programs said EEPROM cell.

### Claim 7 (depends on 1)

The EEPROM cell of claim 1, further comprising:
a word bit line (WBL) electrically coupled to said tunneling drain;
an array control gate (ACG) electrically coupled to said program junction region;
a product term ground (PTG) electrically coupled to said sense source;
a product term (PT) electrically coupled to a read drain of said read transistor; and
a word line read (WLR) electrically coupled to said read transistor, wherein said WBL, ACG, PTG, PT and WLR provide said sufficient voltage potential between said floating gate and said tunneling drain and said sufficient voltage potential between said floating gate and said sense channel.

### Claim 8 (depends on 7)

The EEPROM cell of claim 7, wherein said sufficient voltage potential between said floating gate and said sense channel is accomplished by providing a floating voltage to said WBL, approximately 10 volts to said ACG, approximately 0 volts to said PTG and said PT, and approximately 1.8 volts to said WLR.

### Claim 9 (depends on 7)

The EEPROM cell of claim 7, wherein said sufficient voltage potential between said floating gate and said tunneling drain is accomplished by providing approximately 10 volts to said WBL, approximately 0 volts to said ACG, said PTG and said WLR, and a floating voltage to said PT.

### Claim 10 (depends on 7)

The EEPROM cell of claim 7, wherein said sufficient voltage potential between said floating gate and said tunneling drain is accomplished by providing approximately 10 volts to said WBL, approximately 0 volts to said ACG and said WLR, and a floating voltage to said PTG and said PT.

### Claim 11 (depends on 7)

The EEPROM cell of claim 7, wherein said sense transistor is a depletion mode transistor.

### Claim 12 (depends on 11)

The EEPROM cell of claim 11, wherein a current flows between said sense source and said sense drain when said WBL has a floating voltage, said ACG and said PTG has approximately 0 volts, said WLR has approximately 1.8 volts and said PT has approximately 0.7 volts.

### Claim 13 (depends on 7)

The EEPROM cell of claim 7, wherein said sense transistor is an enhancement mode transistor.

### Claim 14 (depends on 13)

The EEPROM cell of claim 13, wherein a current flows between said sense source and said sense drain when said WBL has a floating voltage, said ACG and said WLR has approximately 1.8 volts, said PTG has approximately 0 volts and said PT has approximately 0.7 volts.

### Claim 15 (depends on 1)

The EEPROM cell of claim 1, wherein said tunnel oxide layer has a thickness of approximately 80 angstroms.

### Claim 16 (depends on 1)

The EEPROM cell of claim 1, wherein said second program junction oxide layer has a thickness of approximately 96 angstroms.

### Claim 17 (depends on 1)

The EEPROM cell of claim 1, wherein said sense tunnel oxide layer has a thickness of approximately 80 angstroms.

### Claim 18

An EEPROM cell, comprising:
a semiconductor substrate, said semiconductor substrate having a P conductivity type;
a tunneling transistor formed in said semiconductor substrate, said tunneling transistor having a tunneling source, a tunneling drain and a tunneling channel between said tunneling source and said tunneling drain, said tunneling drain and said tunneling source having an N conductivity type, said tunneling drain being electrically coupled to a word bit line;
a program junction region formed in said semiconductor substrate, said program junction region separated from said tunneling transistor by a first oxide, said program junction region having said N conductivity type, said program junction region being electrically coupled to an array control gate;
a program junction oxide layer overlying said program junction region;
a sense transistor formed in said semiconductor substrate and separated from said program junction region by a second oxide, said sense transistor having a sense source, a sense drain and a sense channel between said sense source and said sense drain, said sense source and said sense drain having said N conductivity type, said sense source being electrically coupled to a product term ground;
a sense tunnel oxide layer overlying said sense channel, said sense source and said sense drain;
a read transistor formed in said semiconductor substrate, said read transistor electrically coupled to said sense transistor through said sense drain, said read transistor having a read source and a read drain, said read source and said read drain having said N conductivity type, said read drain being electrically coupled to a product term;
a read gate oxide layer overlying said read channel; and
a floating gate overlying said tunnel oxide layer, said program junction oxide layer and said sense tunnel oxide layer, wherein electron tunneling through said tunnel oxide layer overlying an edge of said tunneling drain occurs upon incurrence of a sufficient voltage potential between said floating gate and said tunneling drain, and wherein electron tunneling through said sense tunnel oxide layer overlying said sense channel occurs upon incurrence of a sufficient voltage potential between said floating gate and said sense channel.

### Claim 19 (depends on 18)

The EEPROM cell of claim 18, wherein said read gate oxide layer has a thickness of approximately 35 angstroms.