# US 6,294,809 B1 · Avalanche programmed floating gate memory cell structure with program element in polysilicon

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- Number: US 6,294,809 B1
- Document ID: US6294809B1
- Status: Granted
- Kind: B1
- Application number: 09/221,360
- Filed: 1998-12-28
- Granted: 2001-09-25
- Earliest claimed: 1998-12-28
- Assignees: Vantis Corporation
- Inventors: Stewart G. Logie
- Web page: https://patentgrep.com/patent/US6294809B1

## CPC

- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A non-volatile memory cell structure comprises a floating gate, a reverse breakdown injection element at least partially formed in a polysilicon layer and operatively coupled to the floating gate, and a transistor at least partially formed in a region of a semiconductor substrate, operatively coupled to the floating gate. In a further aspect, a control gate is capacitively coupled to the floating gate and is formed in said polysilicon layer. The reverse breakdown electron injection element comprises a first, second, and third active regions, the first and second regions comprising a first p/n junction, the second and third active regions comprising a second p/n junction.

## Claims

### Claim 1

A non-volatile memory cell structure, comprising:
a floating gate;
a reverse breakdown injection element at least partially formed in a poly-silicon layer and operatively coupled to the floating gate; and
a transistor at least partially formed in a region of a semiconductor substrate, operatively coupled to the floating gate.

### Claim 2 (depends on 1)

The structure as defined in claim 1 further comprising:
a control gate capacitively coupled to the floating gate.

### Claim 3 (depends on 2)

The structure as defined in claim 2 wherein the control gate is formed in said polysilicon layer.

### Claim 4 (depends on 1)

The structure as defined in claim 1 wherein said polysilicon layer comprises a second polysilicon layer, said reverse breakdown injection element is formed in said second polysilicon layer, and said floating gate is formed in a first polysilicon layer.

### Claim 5 (depends on 4)

The structure as defined in claim 4 wherein the first polysilicon layer overlies a portion of the silicon substrate and a portion of a device isolation region in the silicon substrate.

### Claim 6 (depends on 4)

The structure as defined in claim 4 wherein the first poly layer is separated from the substrate by a first oxide layer and the second poly layer is separated from the first poly layer by a second oxide layer.

### Claim 7 (depends on 6)

The structure as defined in claim 6 wherein the first oxide has a thickness of about 70 to 90 Å.

### Claim 8 (depends on 6)

The structure as defined in claim 6 wherein the second oxide has a thickness of about 250 to 350 Å.

### Claim 9 (depends on 1)

The structure as defined in claim 1 wherein the reverse breakdown electron injection element comprises a first, second, and third active regions, the first and second regions comprising a first p/n junction, the second and third active regions comprising a second p/n junction.

### Claim 10 (depends on 9)

The structure as defined in claim 9 wherein said polysilicon layer comprises a second polysilicon layer and the first, second, and third active regions are provided in said second polysilicon layer, and the floating gate is provided in a first polysilicon layer.

### Claim 11 (depends on 10)

The structure as defined in claim 10 wherein the second polysilicon layer overlies at least a portion of the first silicon layer.

### Claim 12 (depends on 11)

The structure as defined in claim 11 wherein a first portion of said first and second polysilicon layers partially overlies a device isolation region in the substrate.

### Claim 13 (depends on 12)

The structure as defined in claim 12 further comprising a control gate, operatively coupled to the floating gate.

### Claim 14 (depends on 13)

The structure as defined in claim 13 wherein the control gate is provided in a second portion of said second polysilicon layer.

### Claim 15 (depends on 14)

The structure as defined in claim 14 wherein the transistor comprises a sense transistor which includes a fourth and fifth active regions formed in said substrate and separated by a channel region.

### Claim 16 (depends on 15)

The structure as defined in claim 15 further including a read transistor having a sixth active region and sharing said fifth active region with said sense transistor.

### Claim 17

A non-volatile memory cell structure, comprising:
a semiconductor substrate having a surface and a doping concentration of a first conductivity type;
a first oxide layer on the surface of the substrate;
a floating gate constructed in a first polysilicon layer on a first portion of the first oxide layer and overlying a first portion of the surface of the substrate;
a second oxide layer on the floating gate;
a control gate formed in a first portion of a second polysilicon layer operatively coupled to a first portion of the floating gate;
an injection element including a p/n junction formed in a second portion of the second polysilicon layer; and
a sense transistor including a first source region, and a first drain region both formed in the substrate, and a portion of the floating gate separated from the first source region and the first drain region by a second portion of said first oxide layer.

### Claim 18 (depends on 17)

The structure of claim 17, further comprising
a read transistor having a second drain region and sharing said first source region, a second portion of said first oxide, and a control gate overlying the second portion of the first oxide.

### Claim 19 (depends on 17)

The structure as defined in claim 17 wherein the first oxide has a thickness of about 70 to 90 Å.

### Claim 20 (depends on 17)

The structure as defined in claim 17 wherein the second oxide has a thickness of about 250 to 350 Å.

### Claim 21 (depends on 17)

The structure as defined in claim 17 wherein the first source region and said first drain are heavily doped impurity regions.

### Claim 22

An EEPROM structure, comprising:
a semiconductor substrate of a first conductivity type having a surface;
a sense transistor including a first source and drain regions formed in the substrate adjacent to the surface of said substrate;
a floating gate positioned adjacent to the surface of the substrate and separated from said surface by a gate oxide layer, the floating gate having a first portion overlying the first transistor and at least a second portion overlying a device isolation region;
an injection element in a polysilicon layer overlying the floating gate and separated from it by an oxide layer;
wherein the injection element is constructed so that a reverse voltage breakdown condition generated in the element adds or removes electrons from the floating gate when an appropriate voltage is applied to the floating gate.

### Claim 23 (depends on 22)

The structure of claim 22 further including a control gate capacitively coupled to the floating gate and coupled to a control gate voltage.

### Claim 24 (depends on 22)

The structure of claim 22 wherein the injection element includes at least a first and a second active regions forming a first PN junction, and the first active region is coupled to a write control voltage and the second active region is coupled to a device control voltage.

### Claim 25 (depends on 24)

The structure of claim 24 wherein the injection element includes a third active region forming a PN junction with the second active region and the third active region is coupled to an erase control voltage.

### Claim 26

A memory array comprising a plurality of memory cells on a semiconductor substrate, comprising:
a plurality array control gate voltage conductors;
a plurality of write bit line conductors;
a plurality of product term gates;
a plurality of word lines;
a plurality of product terms;
an array of memory cells, each cell comprising:
a floating gate formed in a first polysilicon layer coupled to one of said array control gate conductors;
an array control gate formed in a second polysilicon layer overlying the first polysilicon layer and coupled to one of the plurality of array control gate voltage conductors;
a reverse breakdown electron injection element at least partially formed in said second polysilicon layer and operatively coupled to the floating gate, having a first active region coupled to one of said plurality or write bit line conductors and a second active region coupled to one of said plurality of write word lines, the regions forming a PN junction;
a sense transistor comprising a source, drain and channel regions formed in the substrate, and underlying a portion of the floating gate; and
a read transistor at least partially formed in the semiconductor substrate sharing said source of said sense transistor as a drain region and having a source region, and including a control gate coupled to one of said word line conductors.

### Claim 27 (depends on 26)

The memory array of claim 26 wherein the substrate includes a plurality of device isolation regions formed therein, and wherein said reverse breakdown electron injection element of one of said array of memory cells is formed over at least a portion of one of said plurality of device isolation regions.

### Claim 28 (depends on 27)

The memory array of claim 27 wherein at least one of said array control gates of one of said array of memory cells is formed over said portion of one of said plurality of device isolation regions.