# US 6,294,806 B1 · Semiconductor memory device having silicon-on-insulator (SOI) structure and method for fabricating thereof

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- Number: US 6,294,806 B1
- Document ID: US6294806B1
- Status: Granted
- Kind: B1
- Application number: 09/320,214
- Filed: 1999-05-26
- Granted: 2001-09-25
- Earliest claimed: 1998-05-27
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Yun-Gi Kim
- Web page: https://patentgrep.com/patent/US6294806B1

## CPC

- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10B 12/31: {having a storage electrode stacked over the transistor}
- H10B 12/33: {the capacitor extending under the transistor}
- H10D 86/01: Manufacture or treatment
- H10B 12/48: {Data lines or contacts therefor}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 89/211: {Design considerations for internal polarisation (integrated injection logic H10D84/65)}
- Y10S 438/928: Front and rear surface processing
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A SOI semiconductor device including a substrate, a first gate electrode formed on a first surface of the substrate between a source/drain region, a first insulating layer formed on the first gate electrode and the first surface of the substrate, a capacitor formed on the first insulating layer, electrically connected to the source/drain region, a second insulating layer formed on the capacitor and the first insulating layer, a third insulating layer formed on a second surface of the substrate, a body contact conductor line formed on and through the third insulating layer in alignment with the first gate electrode, electrically connected to the substrate aligned with the first gate electrode between the source/drain region, a fourth insulating layer formed on the body contact conductor line and the third insulating layer, and a bit line formed on the fourth insulating layer, electrically connected to the source/drain region of the substrate.

## Claims

### Claim 1

A SOI semiconductor device comprising:
a semiconductor substrate having first and second surfaces opposing each other, the first surface having an active region and an inactive region, said active region including at least a pair of source/drain regions;
a first gate electrode formed on the first surface of the substrate between the at least a pair of source/drain regions;
a first insulating layer formed on the first gate electrode and the first surface of the substrate;
a capacitor formed on the first insulating layer and being electrically connected to one of the at least a pair of source/drain regions;
a second insulating layer formed on the capacitor and the first insulating layer;
a third insulating layer formed on the second surface of the substrate;
a body contact conductor line formed on and through the third insulating layer in alignment with the first gate electrode and being electrically connected to the active region of the substrate aligned with the first gate electrode between the at least a pair of source/drain regions;
a fourth insulating layer formed on the body contact conductor line and the third insulating layer; and
a bit line formed on the fourth insulating layer and being electrically connected to one of the at least a pair of source/drain regions of the substrate.

### Claim 2 (depends on 1)

The SOI semiconductor device as claimed in claim 1, wherein the body contact conductor line further comprises:
a contact plug formed through the third insulating layer and electrically connected to the active region of the substrate aligned with the first gate electrode between the at least a pair of source/drain regions; and
a conductive line formed on the third insulating layer in alignment with the contact plug, wherein the conductive line is overlapping and parallel to the first gate electrode.

### Claim 3 (depends on 1)

The SOI semiconductor device as claimed in claim 1 further comprising:
a handling wafer formed on the second insulating layer.

### Claim 4 (depends on 2)

The SOI semiconductor device as claimed in claim 2 further comprising:
a handling wafer formed on the second insulating layer.

### Claim 5 (depends on 1)

The SOI semiconductor device as claimed in claim 1 further comprising:
a fifth insulating layer formed on the bit line.

### Claim 6 (depends on 4)

The SOI semiconductor device as claimed in claim 4 further comprising:
at least a pair of metal lines formed on the fifth insulating layer.

### Claim 7 (depends on 1)

The SOI semiconductor device as claimed in claim 1 further comprising:
a second gate electrode formed on the first surface of the substrate in alignment with the inactive region of the substrate.

### Claim 8

A SOI semiconductor device comprising:
a semiconductor substrate having first and second surfaces opposing each other, the first surface having an active region and an inactive region, said active region including at least a pair of source/drain regions;
a first gate electrode formed on the first surface of the substrate between the at least a pair of source/drain regions;
a first insulating layer formed on the first gate electrode and the first surface of the substrate;
a capacitor formed on the first insulating layer and being electrically connected to one of the at least a pair of source/drain regions;
a second insulating layer formed on the capacitor and the first insulating layer;
a third insulating layer formed on the second surface of the substrate;
a backgate formed on the third insulating layer in alignment with the first gate electrode and being electrically connected to the first gate electrode;
a fourth insulating layer formed on the backgate and the third insulating layer; and
a bit line formed on the fourth insulating layer and being electrically connected to one of the at least a pair of source/drain regions of the substrate.

### Claim 9 (depends on 8)

The SOI semiconductor device as claimed in claim 8 further comprising:
a handling wafer formed on the second insulating layer.

### Claim 10 (depends on 8)

The SOI semiconductor device as claimed in claim 8 further comprising:
a fifth insulating layer formed on the bit line.

### Claim 11 (depends on 8)

The SOI semiconductor device as claimed in claim 8 further comprising:
at least a pair of metal lines formed on the fifth insulating layer.

### Claim 12 (depends on 8)

The SOI semiconductor device as claimed in claim 8 further comprising:
a second gate electrode formed on the first surface of the substrate in alignment with the inactive region of the substrate.